src/panfrost/midgard/midgard_print.c

   1 /*
   2  * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  */
  23
  24 #include <math.h>
  25
  26 #include "util/bitscan.h"
  27 #include "util/half_float.h"
  28 #include "compiler.h"
  29 #include "helpers.h"
  30 #include "midgard_ops.h"
  31
  32 /* Pretty printer for Midgard IR, for use debugging compiler-internal
  33  * passes like register allocation. The output superficially resembles
  34  * Midgard assembly, with the exception that unit information and such is
  35  * (normally) omitted, and generic indices are usually used instead of
  36  * registers */
  37
  38 static void
  39 mir_print_index(int source)
  40 {
  41         if (source == ~0) {
  42                 printf("_");
  43                 return;
  44         }
  45
  46         if (source >= SSA_FIXED_MINIMUM) {
  47                 /* Specific register */
  48                 int reg = SSA_REG_FROM_FIXED(source);
  49
  50                 /* TODO: Moving threshold */
  51                 if (reg > 16 && reg < 24)
  52                         printf("u%d", 23 - reg);
  53                 else
  54                         printf("r%d", reg);
  55         } else {
  56                 printf("%d", source);
  57         }
  58 }
  59
  60 static const char components[16] = "xyzwefghijklmnop";
  61
  62 static void
  63 mir_print_mask(unsigned mask)
  64 {
  65         printf(".");
  66
  67         for (unsigned i = 0; i < 16; ++i) {
  68                 if (mask & (1 << i))
  69                         putchar(components[i]);
  70         }
  71 }
  72
  73 static void
  74 mir_print_swizzle(unsigned *swizzle, nir_alu_type T)
  75 {
  76         unsigned comps = mir_components_for_type(T);
  77
  78         printf(".");
  79
  80         for (unsigned i = 0; i < comps; ++i) {
  81                 unsigned C = swizzle[i];
  82                 assert(C < comps);
  83                 putchar(components[C]);
  84         }
  85 }
  86
  87 static const char *
  88 mir_get_unit(unsigned unit)
  89 {
  90         switch (unit) {
  91         case ALU_ENAB_VEC_MUL:
  92                 return "vmul";
  93         case ALU_ENAB_SCAL_ADD:
  94                 return "sadd";
  95         case ALU_ENAB_VEC_ADD:
  96                 return "vadd";
  97         case ALU_ENAB_SCAL_MUL:
  98                 return "smul";
  99         case ALU_ENAB_VEC_LUT:
 100                 return "lut";
 101         case ALU_ENAB_BR_COMPACT:
 102                 return "br";
 103         case ALU_ENAB_BRANCH:
 104                 return "brx";
 105         default:
 106                 return "???";
 107         }
 108 }
 109
 110 void
 111 mir_print_constant_component(FILE *fp, const midgard_constants *consts, unsigned c,
 112                              midgard_reg_mode reg_mode, bool half,
 113                              unsigned mod, midgard_alu_op op)
 114 {
 115         bool is_sint = false, is_uint = false, is_hex = false;
 116         const char *opname = alu_opcode_props[op].name;
 117
 118         /* Add a sentinel name to prevent crashing */
 119         if (!opname)
 120                 opname = "unknown";
 121
 122         if (opname[0] == 'u') {
 123                 /* If the opcode starts with a 'u' we are sure we deal with an
 124                  * unsigned int operation
 125                  */
 126                 is_uint = true;
 127         } else if (opname[0] == 'i') {
 128                 /* Bit ops are easier to follow when the constant is printed in
 129                  * hexadecimal. Other operations starting with a 'i' are
 130                  * considered to operate on signed integers. That might not
 131                  * be true for all of them, but it's good enough for traces.
 132                  */
 133                 if (op >= midgard_alu_op_iand &&
 134                     op <= midgard_alu_op_ibitcount8)
 135                         is_hex = true;
 136                 else
 137                         is_sint = true;
 138         }
 139
 140         if (half)
 141                 reg_mode--;
 142
 143         switch (reg_mode) {
 144         case midgard_reg_mode_64:
 145                 if (is_sint) {
 146                         fprintf(fp, "%"PRIi64, consts->i64[c]);
 147                 } else if (is_uint) {
 148                         fprintf(fp, "%"PRIu64, consts->u64[c]);
 149                 } else if (is_hex) {
 150                         fprintf(fp, "0x%"PRIX64, consts->u64[c]);
 151                 } else {
 152                         double v = consts->f64[c];
 153
 154                         if (mod & MIDGARD_FLOAT_MOD_ABS) v = fabs(v);
 155                         if (mod & MIDGARD_FLOAT_MOD_NEG) v = -v;
 156
 157                         printf("%g", v);
 158                 }
 159                 break;
 160
 161         case midgard_reg_mode_32:
 162                 if (is_sint) {
 163                         int64_t v;
 164
 165                         if (half && mod == midgard_int_zero_extend)
 166                                 v = consts->u32[c];
 167                         else if (half && mod == midgard_int_shift)
 168                                 v = (uint64_t)consts->u32[c] << 32;
 169                         else
 170                                 v = consts->i32[c];
 171
 172                         fprintf(fp, "%"PRIi64, v);
 173                 } else if (is_uint || is_hex) {
 174                         uint64_t v;
 175
 176                         if (half && mod == midgard_int_shift)
 177                                 v = (uint64_t)consts->u32[c] << 32;
 178                         else
 179                                 v = consts->u32[c];
 180
 181                         fprintf(fp, is_uint ? "%"PRIu64 : "0x%"PRIX64, v);
 182                 } else {
 183                         float v = consts->f32[c];
 184
 185                         if (mod & MIDGARD_FLOAT_MOD_ABS) v = fabsf(v);
 186                         if (mod & MIDGARD_FLOAT_MOD_NEG) v = -v;
 187
 188                         fprintf(fp, "%g", v);
 189                 }
 190                 break;
 191
 192         case midgard_reg_mode_16:
 193                 if (is_sint) {
 194                         int32_t v;
 195
 196                         if (half && mod == midgard_int_zero_extend)
 197                                 v = consts->u16[c];
 198                         else if (half && mod == midgard_int_shift)
 199                                 v = (uint32_t)consts->u16[c] << 16;
 200                         else
 201                                 v = consts->i16[c];
 202
 203                         fprintf(fp, "%d", v);
 204                 } else if (is_uint || is_hex) {
 205                         uint32_t v;
 206
 207                         if (half && mod == midgard_int_shift)
 208                                 v = (uint32_t)consts->u16[c] << 16;
 209                         else
 210                                 v = consts->u16[c];
 211
 212                         fprintf(fp, is_uint ? "%u" : "0x%X", v);
 213                 } else {
 214                         float v = _mesa_half_to_float(consts->f16[c]);
 215
 216                         if (mod & MIDGARD_FLOAT_MOD_ABS) v = fabsf(v);
 217                         if (mod & MIDGARD_FLOAT_MOD_NEG) v = -v;
 218
 219                         fprintf(fp, "%g", v);
 220                 }
 221                 break;
 222
 223         case midgard_reg_mode_8:
 224                 fprintf(fp, "0x%X", consts->u8[c]);
 225
 226                 if (mod)
 227                         fprintf(fp, " /* %u */", mod);
 228
 229                 assert(!half); /* No 4-bit */
 230
 231                 break;
 232         }
 233 }
 234
 235 static void
 236 mir_print_embedded_constant(midgard_instruction *ins, unsigned src_idx)
 237 {
 238         midgard_vector_alu_src src;
 239
 240         assert(src_idx <= 1);
 241         if (src_idx == 0)
 242                 src = vector_alu_from_unsigned(ins->alu.src1);
 243         else
 244                 src = vector_alu_from_unsigned(ins->alu.src2);
 245
 246         unsigned *swizzle = ins->swizzle[src_idx];
 247         unsigned comp_mask = effective_writemask(&ins->alu, ins->mask);
 248         unsigned num_comp = util_bitcount(comp_mask);
 249         unsigned max_comp = mir_components_for_type(ins->dest_type) >> 1;
 250         bool first = true;
 251
 252         printf("#");
 253
 254         if (num_comp > 1)
 255                 printf("vec%d(", num_comp);
 256
 257         for (unsigned comp = 0; comp < max_comp; comp++) {
 258                 if (!(comp_mask & (1 << comp)))
 259                         continue;
 260
 261                 if (first)
 262                         first = false;
 263                 else
 264                         printf(", ");
 265
 266                 mir_print_constant_component(stdout, &ins->constants,
 267                                              swizzle[comp], ins->alu.reg_mode,
 268                                              src.half, src.mod, ins->alu.op);
 269         }
 270
 271         if (num_comp > 1)
 272                 printf(")");
 273 }
 274
 275 #define PRINT_SRC(ins, c) \
 276         do { mir_print_index(ins->src[c]); \
 277              if (ins->src[c] != ~0 && ins->src_types[c] != nir_type_invalid) { \
 278                      pan_print_alu_type(ins->src_types[c], stdout); \
 279                      mir_print_swizzle(ins->swizzle[c], ins->src_types[c]); \
 280              } } while (0)
 281
 282 void
 283 mir_print_instruction(midgard_instruction *ins)
 284 {
 285         printf("\t");
 286
 287         if (midgard_is_branch_unit(ins->unit)) {
 288                 const char *branch_target_names[] = {
 289                         "goto", "break", "continue", "discard"
 290                 };
 291
 292                 printf("%s.", mir_get_unit(ins->unit));
 293                 if (ins->branch.target_type == TARGET_DISCARD)
 294                         printf("discard.");
 295                 else if (ins->writeout)
 296                         printf("write.");
 297                 else if (ins->unit == ALU_ENAB_BR_COMPACT &&
 298                          !ins->branch.conditional)
 299                         printf("uncond.");
 300                 else
 301                         printf("cond.");
 302
 303                 if (!ins->branch.conditional)
 304                         printf("always");
 305                 else if (ins->branch.invert_conditional)
 306                         printf("false");
 307                 else
 308                         printf("true");
 309
 310                 if (ins->branch.target_type != TARGET_DISCARD)
 311                         printf(" %s -> block(%d)\n",
 312                                ins->branch.target_type < 4 ?
 313                                        branch_target_names[ins->branch.target_type] : "??",
 314                                ins->branch.target_block);
 315
 316                 return;
 317         }
 318
 319         switch (ins->type) {
 320         case TAG_ALU_4: {
 321                 midgard_alu_op op = ins->alu.op;
 322                 const char *name = alu_opcode_props[op].name;
 323
 324                 if (ins->unit)
 325                         printf("%s.", mir_get_unit(ins->unit));
 326
 327                 printf("%s", name ? name : "??");
 328                 break;
 329         }
 330
 331         case TAG_LOAD_STORE_4: {
 332                 midgard_load_store_op op = ins->load_store.op;
 333                 const char *name = load_store_opcode_props[op].name;
 334
 335                 assert(name);
 336                 printf("%s", name);
 337                 break;
 338         }
 339
 340         case TAG_TEXTURE_4: {
 341                 printf("texture");
 342
 343                 if (ins->helper_terminate)
 344                         printf(".terminate");
 345
 346                 if (ins->helper_execute)
 347                         printf(".execute");
 348
 349                 break;
 350         }
 351
 352         default:
 353                 assert(0);
 354         }
 355
 356         if (ins->compact_branch && ins->branch.invert_conditional)
 357                 printf(".not");
 358
 359         printf(" ");
 360         mir_print_index(ins->dest);
 361
 362         if (ins->dest != ~0) {
 363                 pan_print_alu_type(ins->dest_type, stdout);
 364                 mir_print_mask(ins->mask);
 365         }
 366
 367         printf(", ");
 368
 369         unsigned r_constant = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
 370
 371         if (ins->src[0] == r_constant)
 372                 mir_print_embedded_constant(ins, 0);
 373         else
 374                 PRINT_SRC(ins, 0);
 375
 376         printf(", ");
 377
 378         if (ins->has_inline_constant)
 379                 printf("#%d", ins->inline_constant);
 380         else if (ins->src[1] == r_constant)
 381                 mir_print_embedded_constant(ins, 1);
 382         else
 383                 PRINT_SRC(ins, 1);
 384
 385         for (unsigned c = 2; c <= 3; ++c) {
 386                 printf(", ");
 387                 PRINT_SRC(ins, c);
 388         }
 389
 390         if (ins->no_spill)
 391                 printf(" /* no spill */");
 392
 393         printf("\n");
 394 }
 395
 396 /* Dumps MIR for a block or entire shader respective */
 397
 398 void
 399 mir_print_block(midgard_block *block)
 400 {
 401         printf("block%u: {\n", block->base.name);
 402
 403         if (block->scheduled) {
 404                 mir_foreach_bundle_in_block(block, bundle) {
 405                         for (unsigned i = 0; i < bundle->instruction_count; ++i)
 406                                 mir_print_instruction(bundle->instructions[i]);
 407
 408                         printf("\n");
 409                 }
 410         } else {
 411                 mir_foreach_instr_in_block(block, ins) {
 412                         mir_print_instruction(ins);
 413                 }
 414         }
 415
 416         printf("}");
 417
 418         if (block->base.successors[0]) {
 419                 printf(" -> ");
 420                 pan_foreach_successor((&block->base), succ)
 421                         printf(" block%u ", succ->name);
 422         }
 423
 424         printf(" from { ");
 425         mir_foreach_predecessor(block, pred)
 426                 printf("block%u ", pred->base.name);
 427         printf("}");
 428
 429         printf("\n\n");
 430 }
 431
 432 void
 433 mir_print_shader(compiler_context *ctx)
 434 {
 435         mir_foreach_block(ctx, block) {
 436                 mir_print_block((midgard_block *) block);
 437         }
 438 }