2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 #include "util/bitscan.h"
27 #include "util/half_float.h"
30 #include "midgard_ops.h"
32 /* Pretty printer for Midgard IR, for use debugging compiler-internal
33 * passes like register allocation. The output superficially resembles
34 * Midgard assembly, with the exception that unit information and such is
35 * (normally) omitted, and generic indices are usually used instead of
39 mir_print_index(int source
)
46 if (source
>= SSA_FIXED_MINIMUM
) {
47 /* Specific register */
48 int reg
= SSA_REG_FROM_FIXED(source
);
50 /* TODO: Moving threshold */
51 if (reg
> 16 && reg
< 24)
52 printf("u%d", 23 - reg
);
60 static const char components
[16] = "xyzwefghijklmnop";
63 mir_print_mask(unsigned mask
)
67 for (unsigned i
= 0; i
< 16; ++i
) {
69 putchar(components
[i
]);
74 mir_print_swizzle(unsigned *swizzle
, nir_alu_type T
)
76 unsigned comps
= mir_components_for_type(T
);
80 for (unsigned i
= 0; i
< comps
; ++i
) {
81 unsigned C
= swizzle
[i
];
83 putchar(components
[C
]);
88 mir_get_unit(unsigned unit
)
91 case ALU_ENAB_VEC_MUL
:
93 case ALU_ENAB_SCAL_ADD
:
95 case ALU_ENAB_VEC_ADD
:
97 case ALU_ENAB_SCAL_MUL
:
99 case ALU_ENAB_VEC_LUT
:
101 case ALU_ENAB_BR_COMPACT
:
103 case ALU_ENAB_BRANCH
:
111 mir_print_constant_component(FILE *fp
, const midgard_constants
*consts
, unsigned c
,
112 midgard_reg_mode reg_mode
, bool half
,
113 unsigned mod
, midgard_alu_op op
)
115 bool is_sint
= false, is_uint
= false, is_hex
= false;
116 const char *opname
= alu_opcode_props
[op
].name
;
118 /* Add a sentinel name to prevent crashing */
122 if (opname
[0] == 'u') {
123 /* If the opcode starts with a 'u' we are sure we deal with an
124 * unsigned int operation
127 } else if (opname
[0] == 'i') {
128 /* Bit ops are easier to follow when the constant is printed in
129 * hexadecimal. Other operations starting with a 'i' are
130 * considered to operate on signed integers. That might not
131 * be true for all of them, but it's good enough for traces.
133 if (op
>= midgard_alu_op_iand
&&
134 op
<= midgard_alu_op_ibitcount8
)
144 case midgard_reg_mode_64
:
146 fprintf(fp
, "%"PRIi64
, consts
->i64
[c
]);
147 } else if (is_uint
) {
148 fprintf(fp
, "%"PRIu64
, consts
->u64
[c
]);
150 fprintf(fp
, "0x%"PRIX64
, consts
->u64
[c
]);
152 double v
= consts
->f64
[c
];
154 if (mod
& MIDGARD_FLOAT_MOD_ABS
) v
= fabs(v
);
155 if (mod
& MIDGARD_FLOAT_MOD_NEG
) v
= -v
;
161 case midgard_reg_mode_32
:
165 if (half
&& mod
== midgard_int_zero_extend
)
167 else if (half
&& mod
== midgard_int_shift
)
168 v
= (uint64_t)consts
->u32
[c
] << 32;
172 fprintf(fp
, "%"PRIi64
, v
);
173 } else if (is_uint
|| is_hex
) {
176 if (half
&& mod
== midgard_int_shift
)
177 v
= (uint64_t)consts
->u32
[c
] << 32;
181 fprintf(fp
, is_uint
? "%"PRIu64
: "0x%"PRIX64
, v
);
183 float v
= consts
->f32
[c
];
185 if (mod
& MIDGARD_FLOAT_MOD_ABS
) v
= fabsf(v
);
186 if (mod
& MIDGARD_FLOAT_MOD_NEG
) v
= -v
;
188 fprintf(fp
, "%g", v
);
192 case midgard_reg_mode_16
:
196 if (half
&& mod
== midgard_int_zero_extend
)
198 else if (half
&& mod
== midgard_int_shift
)
199 v
= (uint32_t)consts
->u16
[c
] << 16;
203 fprintf(fp
, "%d", v
);
204 } else if (is_uint
|| is_hex
) {
207 if (half
&& mod
== midgard_int_shift
)
208 v
= (uint32_t)consts
->u16
[c
] << 16;
212 fprintf(fp
, is_uint
? "%u" : "0x%X", v
);
214 float v
= _mesa_half_to_float(consts
->f16
[c
]);
216 if (mod
& MIDGARD_FLOAT_MOD_ABS
) v
= fabsf(v
);
217 if (mod
& MIDGARD_FLOAT_MOD_NEG
) v
= -v
;
219 fprintf(fp
, "%g", v
);
223 case midgard_reg_mode_8
:
224 fprintf(fp
, "0x%X", consts
->u8
[c
]);
227 fprintf(fp
, " /* %u */", mod
);
229 assert(!half
); /* No 4-bit */
236 mir_print_embedded_constant(midgard_instruction
*ins
, unsigned src_idx
)
238 midgard_vector_alu_src src
;
240 assert(src_idx
<= 1);
242 src
= vector_alu_from_unsigned(ins
->alu
.src1
);
244 src
= vector_alu_from_unsigned(ins
->alu
.src2
);
246 unsigned *swizzle
= ins
->swizzle
[src_idx
];
247 unsigned comp_mask
= effective_writemask(ins
->op
, ins
->mask
);
248 unsigned num_comp
= util_bitcount(comp_mask
);
249 unsigned max_comp
= mir_components_for_type(ins
->dest_type
);
255 printf("vec%d(", num_comp
);
257 for (unsigned comp
= 0; comp
< max_comp
; comp
++) {
258 if (!(comp_mask
& (1 << comp
)))
266 mir_print_constant_component(stdout
, &ins
->constants
,
267 swizzle
[comp
], ins
->alu
.reg_mode
,
268 src
.half
, src
.mod
, ins
->op
);
275 #define PRINT_SRC(ins, c) \
276 do { mir_print_index(ins->src[c]); \
277 if (ins->src[c] != ~0 && ins->src_types[c] != nir_type_invalid) { \
278 pan_print_alu_type(ins->src_types[c], stdout); \
279 mir_print_swizzle(ins->swizzle[c], ins->src_types[c]); \
283 mir_print_instruction(midgard_instruction
*ins
)
287 if (midgard_is_branch_unit(ins
->unit
)) {
288 const char *branch_target_names
[] = {
289 "goto", "break", "continue", "discard"
292 printf("%s.", mir_get_unit(ins
->unit
));
293 if (ins
->branch
.target_type
== TARGET_DISCARD
)
295 else if (ins
->writeout
)
297 else if (ins
->unit
== ALU_ENAB_BR_COMPACT
&&
298 !ins
->branch
.conditional
)
303 if (!ins
->branch
.conditional
)
305 else if (ins
->branch
.invert_conditional
)
320 if (ins
->branch
.target_type
!= TARGET_DISCARD
)
321 printf(" %s -> block(%d)\n",
322 ins
->branch
.target_type
< 4 ?
323 branch_target_names
[ins
->branch
.target_type
] : "??",
324 ins
->branch
.target_block
);
331 midgard_alu_op op
= ins
->op
;
332 const char *name
= alu_opcode_props
[op
].name
;
335 printf("%s.", mir_get_unit(ins
->unit
));
337 printf("%s", name
? name
: "??");
341 case TAG_LOAD_STORE_4
: {
342 midgard_load_store_op op
= ins
->load_store
.op
;
343 const char *name
= load_store_opcode_props
[op
].name
;
350 case TAG_TEXTURE_4
: {
353 if (ins
->helper_terminate
)
354 printf(".terminate");
356 if (ins
->helper_execute
)
366 if (ins
->compact_branch
&& ins
->branch
.invert_conditional
)
370 mir_print_index(ins
->dest
);
372 if (ins
->dest
!= ~0) {
373 pan_print_alu_type(ins
->dest_type
, stdout
);
374 mir_print_mask(ins
->mask
);
379 unsigned r_constant
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
381 if (ins
->src
[0] == r_constant
)
382 mir_print_embedded_constant(ins
, 0);
388 if (ins
->has_inline_constant
)
389 printf("#%d", ins
->inline_constant
);
390 else if (ins
->src
[1] == r_constant
)
391 mir_print_embedded_constant(ins
, 1);
395 for (unsigned c
= 2; c
<= 3; ++c
) {
401 printf(" /* no spill */");
406 /* Dumps MIR for a block or entire shader respective */
409 mir_print_block(midgard_block
*block
)
411 printf("block%u: {\n", block
->base
.name
);
413 if (block
->scheduled
) {
414 mir_foreach_bundle_in_block(block
, bundle
) {
415 for (unsigned i
= 0; i
< bundle
->instruction_count
; ++i
)
416 mir_print_instruction(bundle
->instructions
[i
]);
421 mir_foreach_instr_in_block(block
, ins
) {
422 mir_print_instruction(ins
);
428 if (block
->base
.successors
[0]) {
430 pan_foreach_successor((&block
->base
), succ
)
431 printf(" block%u ", succ
->name
);
435 mir_foreach_predecessor(block
, pred
)
436 printf("block%u ", pred
->base
.name
);
443 mir_print_shader(compiler_context
*ctx
)
445 mir_foreach_block(ctx
, block
) {
446 mir_print_block((midgard_block
*) block
);