2 * Copyright (C) 2019 Collabora, Ltd.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #ifndef __MDG_QUIRKS_H
25 #define __MDG_QUIRKS_H
27 /* Model-specific quirks requiring compiler workarounds/etc. Quirks
28 * may be errata requiring a workaround, or features. We're trying to be
29 * quirk-positive here; quirky is the best! */
31 /* Whether an explicit LOD is required via textureLod in a vertex shader. If
32 * set, vertex texturing will *always* textureLod. If unset, normal texture ops
33 * may be emitted in a vertex shader */
35 #define MIDGARD_EXPLICIT_LOD (1 << 0)
37 /* Whether output texture registers (normally r28/r29) overlap with work
38 * registers r0/r1 and input texture registers (also normally r28/r29) overlap
39 * with load/store registers r26/r27. This constrains register allocation
40 * considerably but is a space-saving measure on small Midgards. It's worth
41 * noting if you try to access r28/r29, it may still work, but you'll mess up
42 * the interference. Corresponds to BASE_HW_FEATURE_INTERPIPE_REG_ALIASING in
45 #define MIDGARD_INTERPIPE_REG_ALIASING (1 << 1)
47 /* Whether we should use old-style blend opcodes */
49 #define MIDGARD_OLD_BLEND (1 << 2)
51 /* Errata causing the LOD clamps and bias in the sampler descriptor to be
52 * ignored. This errata affects the command stream but uses a compiler
53 * workaround (applying the clamps/bias manually in the shader. Corresponds in
54 * BASE_HW_ISSUE_10471 in kbase, described as "TEXGRD doesn't honor Sampler
55 * Descriptor LOD clamps nor bias". (I'm assuming TEXGRD is what we call
58 #define MIDGARD_BROKEN_LOD (1 << 3)
60 /* Don't use upper ALU tags for writeout (if you do, you'll get a
61 * INSTR_INVALID_ENC). It's not clear to me what these tags are for. */
63 #define MIDGARD_NO_UPPER_ALU (1 << 4)
65 static inline unsigned
66 midgard_get_quirks(unsigned gpu_id
)
71 return MIDGARD_OLD_BLEND
|
76 return MIDGARD_INTERPIPE_REG_ALIASING
|
83 return MIDGARD_INTERPIPE_REG_ALIASING
;
86 return MIDGARD_EXPLICIT_LOD
|
91 return MIDGARD_EXPLICIT_LOD
;
94 unreachable("Invalid Midgard GPU ID");