2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
3 * Copyright (C) 2019 Collabora, Ltd.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 #include "midgard_ops.h"
27 #include "util/register_allocate.h"
28 #include "util/u_math.h"
30 /* For work registers, we can subdivide in various ways. So we create
31 * classes for the various sizes and conflict accordingly, keeping in
32 * mind that physical registers are divided along 128-bit boundaries.
33 * The important part is that 128-bit boundaries are not crossed.
35 * For each 128-bit register, we can subdivide to 32-bits 10 ways
42 * For each 64-bit register, we can subdivide similarly to 16-bit
43 * (TODO: half-float RA, not that we support fp16 yet)
46 #define WORK_STRIDE 10
48 /* We have overlapping register classes for special registers, handled via
55 /* Prepacked masks/swizzles for virtual register types */
56 static unsigned reg_type_to_mask
[WORK_STRIDE
] = {
58 0x7, 0x7 << 1, /* xyz */
59 0x3, 0x3 << 1, 0x3 << 2, /* xy */
60 0x1, 0x1 << 1, 0x1 << 2, 0x1 << 3 /* x */
63 static unsigned reg_type_to_swizzle
[WORK_STRIDE
] = {
64 SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
66 SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
67 SWIZZLE(COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
, COMPONENT_W
),
69 SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
70 SWIZZLE(COMPONENT_Y
, COMPONENT_Z
, COMPONENT_Z
, COMPONENT_W
),
71 SWIZZLE(COMPONENT_Z
, COMPONENT_W
, COMPONENT_Z
, COMPONENT_W
),
73 SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
74 SWIZZLE(COMPONENT_Y
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
75 SWIZZLE(COMPONENT_Z
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
76 SWIZZLE(COMPONENT_W
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
85 /* Given the mask/swizzle of both the register and the original source,
86 * compose to find the actual mask/swizzle to give the hardware */
89 compose_writemask(unsigned mask
, struct phys_reg reg
)
91 /* Note: the reg mask is guaranteed to be contiguous. So we shift
92 * into the X place, compose via a simple AND, and shift back */
94 unsigned shift
= __builtin_ctz(reg
.mask
);
95 return ((reg
.mask
>> shift
) & mask
) << shift
;
99 compose_swizzle(unsigned swizzle
, unsigned mask
,
100 struct phys_reg reg
, struct phys_reg dst
)
102 unsigned out
= pan_compose_swizzle(swizzle
, reg
.swizzle
);
104 /* Based on the register mask, we need to adjust over. E.g if we're
105 * writing to yz, a base swizzle of xy__ becomes _xy_. Save the
106 * original first component (x). But to prevent duplicate shifting
107 * (only applies to ALU -- mask param is set to xyzw out on L/S to
108 * prevent changes), we have to account for the shift inherent to the
109 * original writemask */
111 unsigned rep
= out
& 0x3;
112 unsigned shift
= __builtin_ctz(dst
.mask
) - __builtin_ctz(mask
);
113 unsigned shifted
= out
<< (2*shift
);
115 /* ..but we fill in the gaps so it appears to replicate */
117 for (unsigned s
= 0; s
< shift
; ++s
)
118 shifted
|= rep
<< (2*s
);
123 /* Helper to return the default phys_reg for a given register */
125 static struct phys_reg
126 default_phys_reg(int reg
)
128 struct phys_reg r
= {
130 .mask
= 0xF, /* xyzw */
131 .swizzle
= 0xE4 /* xyzw */
137 /* Determine which physical register, swizzle, and mask a virtual
138 * register corresponds to */
140 static struct phys_reg
141 index_to_reg(compiler_context
*ctx
, struct ra_graph
*g
, unsigned reg
)
143 /* Check for special cases */
145 return default_phys_reg(REGISTER_UNUSED
);
146 else if (reg
>= SSA_FIXED_MINIMUM
)
147 return default_phys_reg(SSA_REG_FROM_FIXED(reg
));
149 return default_phys_reg(REGISTER_UNUSED
);
151 /* Special cases aside, we pick the underlying register */
152 int virt
= ra_get_node_reg(g
, reg
);
154 /* Divide out the register and classification */
155 int phys
= virt
/ WORK_STRIDE
;
156 int type
= virt
% WORK_STRIDE
;
158 /* Apply shadow registers */
160 if (phys
>= SHADOW_R28
&& phys
<= SHADOW_R29
)
161 phys
+= 28 - SHADOW_R28
;
162 else if (phys
== SHADOW_R0
)
165 struct phys_reg r
= {
167 .mask
= reg_type_to_mask
[type
],
168 .swizzle
= reg_type_to_swizzle
[type
]
171 /* Report that we actually use this register, and return it */
174 ctx
->work_registers
= MAX2(ctx
->work_registers
, phys
);
179 /* This routine creates a register set. Should be called infrequently since
180 * it's slow and can be cached. For legibility, variables are named in terms of
181 * work registers, although it is also used to create the register set for
182 * special register allocation */
185 add_shadow_conflicts (struct ra_regs
*regs
, unsigned base
, unsigned shadow
, unsigned shadow_count
)
187 for (unsigned a
= 0; a
< WORK_STRIDE
; ++a
) {
188 unsigned reg_a
= (WORK_STRIDE
* base
) + a
;
190 for (unsigned b
= 0; b
< shadow_count
; ++b
) {
191 unsigned reg_b
= (WORK_STRIDE
* shadow
) + b
;
193 ra_add_reg_conflict(regs
, reg_a
, reg_b
);
194 ra_add_reg_conflict(regs
, reg_b
, reg_a
);
199 static struct ra_regs
*
200 create_register_set(unsigned work_count
, unsigned *classes
)
202 int virtual_count
= 32 * WORK_STRIDE
;
204 /* First, initialize the RA */
205 struct ra_regs
*regs
= ra_alloc_reg_set(NULL
, virtual_count
, true);
207 for (unsigned c
= 0; c
< (NR_REG_CLASSES
- 1); ++c
) {
208 int work_vec4
= ra_alloc_reg_class(regs
);
209 int work_vec3
= ra_alloc_reg_class(regs
);
210 int work_vec2
= ra_alloc_reg_class(regs
);
211 int work_vec1
= ra_alloc_reg_class(regs
);
213 classes
[4*c
+ 0] = work_vec1
;
214 classes
[4*c
+ 1] = work_vec2
;
215 classes
[4*c
+ 2] = work_vec3
;
216 classes
[4*c
+ 3] = work_vec4
;
218 /* Special register classes have other register counts */
220 (c
== REG_CLASS_WORK
) ? work_count
: 2;
223 (c
== REG_CLASS_LDST
) ? 26 :
224 (c
== REG_CLASS_TEXR
) ? 28 :
225 (c
== REG_CLASS_TEXW
) ? SHADOW_R28
:
228 /* Add the full set of work registers */
229 for (unsigned i
= first_reg
; i
< (first_reg
+ count
); ++i
) {
230 int base
= WORK_STRIDE
* i
;
232 /* Build a full set of subdivisions */
233 ra_class_add_reg(regs
, work_vec4
, base
);
234 ra_class_add_reg(regs
, work_vec3
, base
+ 1);
235 ra_class_add_reg(regs
, work_vec3
, base
+ 2);
236 ra_class_add_reg(regs
, work_vec2
, base
+ 3);
237 ra_class_add_reg(regs
, work_vec2
, base
+ 4);
238 ra_class_add_reg(regs
, work_vec2
, base
+ 5);
239 ra_class_add_reg(regs
, work_vec1
, base
+ 6);
240 ra_class_add_reg(regs
, work_vec1
, base
+ 7);
241 ra_class_add_reg(regs
, work_vec1
, base
+ 8);
242 ra_class_add_reg(regs
, work_vec1
, base
+ 9);
244 for (unsigned a
= 0; a
< 10; ++a
) {
245 unsigned mask1
= reg_type_to_mask
[a
];
247 for (unsigned b
= 0; b
< 10; ++b
) {
248 unsigned mask2
= reg_type_to_mask
[b
];
251 ra_add_reg_conflict(regs
,
258 int fragc
= ra_alloc_reg_class(regs
);
260 classes
[4*REG_CLASS_FRAGC
+ 0] = fragc
;
261 classes
[4*REG_CLASS_FRAGC
+ 1] = fragc
;
262 classes
[4*REG_CLASS_FRAGC
+ 2] = fragc
;
263 classes
[4*REG_CLASS_FRAGC
+ 3] = fragc
;
264 ra_class_add_reg(regs
, fragc
, WORK_STRIDE
* SHADOW_R0
);
266 /* We have duplicate classes */
267 add_shadow_conflicts(regs
, 0, SHADOW_R0
, 1);
268 add_shadow_conflicts(regs
, 28, SHADOW_R28
, WORK_STRIDE
);
269 add_shadow_conflicts(regs
, 29, SHADOW_R29
, WORK_STRIDE
);
271 /* We're done setting up */
272 ra_set_finalize(regs
, NULL
);
277 /* This routine gets a precomputed register set off the screen if it's able, or
278 * otherwise it computes one on the fly */
280 static struct ra_regs
*
281 get_register_set(struct midgard_screen
*screen
, unsigned work_count
, unsigned **classes
)
284 assert(work_count
>= 8);
285 assert(work_count
<= 16);
288 unsigned index
= work_count
- 8;
290 /* Find the reg set */
291 struct ra_regs
*cached
= screen
->regs
[index
];
294 assert(screen
->reg_classes
[index
]);
295 *classes
= screen
->reg_classes
[index
];
299 /* Otherwise, create one */
300 struct ra_regs
*created
= create_register_set(work_count
, screen
->reg_classes
[index
]);
302 /* Cache it and use it */
303 screen
->regs
[index
] = created
;
305 *classes
= screen
->reg_classes
[index
];
309 /* Assign a (special) class, ensuring that it is compatible with whatever class
313 set_class(unsigned *classes
, unsigned node
, unsigned class)
315 /* Check that we're even a node */
316 if (node
>= SSA_FIXED_MINIMUM
)
319 /* First 4 are work, next 4 are load/store.. */
320 unsigned current_class
= classes
[node
] >> 2;
323 if (class == current_class
)
326 /* If we're changing, we haven't assigned a special class */
327 assert(current_class
== REG_CLASS_WORK
);
329 classes
[node
] &= 0x3;
330 classes
[node
] |= (class << 2);
334 force_vec4(unsigned *classes
, unsigned node
)
336 if (node
>= SSA_FIXED_MINIMUM
)
340 classes
[node
] |= 0x3;
343 /* Special register classes impose special constraints on who can read their
344 * values, so check that */
347 check_read_class(unsigned *classes
, unsigned tag
, unsigned node
)
349 /* Non-nodes are implicitly ok */
350 if (node
>= SSA_FIXED_MINIMUM
)
353 unsigned current_class
= classes
[node
] >> 2;
355 switch (current_class
) {
357 return (tag
== TAG_LOAD_STORE_4
);
359 return (tag
== TAG_TEXTURE_4
);
361 return (tag
!= TAG_LOAD_STORE_4
);
365 unreachable("Invalid class");
370 check_write_class(unsigned *classes
, unsigned tag
, unsigned node
)
372 /* Non-nodes are implicitly ok */
373 if (node
>= SSA_FIXED_MINIMUM
)
376 unsigned current_class
= classes
[node
] >> 2;
378 switch (current_class
) {
382 return (tag
== TAG_TEXTURE_4
);
385 return IS_ALU(tag
) || (tag
== TAG_LOAD_STORE_4
);
387 unreachable("Invalid class");
391 /* Prepass before RA to ensure special class restrictions are met. The idea is
392 * to create a bit field of types of instructions that read a particular index.
393 * Later, we'll add moves as appropriate and rewrite to specialize by type. */
396 mark_node_class (unsigned *bitfield
, unsigned node
)
398 if (node
< SSA_FIXED_MINIMUM
)
399 BITSET_SET(bitfield
, node
);
403 mir_lower_special_reads(compiler_context
*ctx
)
405 size_t sz
= BITSET_WORDS(ctx
->temp_count
) * sizeof(BITSET_WORD
);
407 /* Bitfields for the various types of registers we could have. aluw can
408 * be written by either ALU or load/store */
410 unsigned *alur
= calloc(sz
, 1);
411 unsigned *aluw
= calloc(sz
, 1);
412 unsigned *brar
= calloc(sz
, 1);
413 unsigned *ldst
= calloc(sz
, 1);
414 unsigned *texr
= calloc(sz
, 1);
415 unsigned *texw
= calloc(sz
, 1);
417 /* Pass #1 is analysis, a linear scan to fill out the bitfields */
419 mir_foreach_instr_global(ctx
, ins
) {
422 mark_node_class(aluw
, ins
->dest
);
423 mark_node_class(alur
, ins
->src
[0]);
424 mark_node_class(alur
, ins
->src
[1]);
425 mark_node_class(alur
, ins
->src
[2]);
427 if (ins
->compact_branch
&& ins
->writeout
)
428 mark_node_class(brar
, ins
->src
[0]);
432 case TAG_LOAD_STORE_4
:
433 mark_node_class(aluw
, ins
->dest
);
434 mark_node_class(ldst
, ins
->src
[0]);
435 mark_node_class(ldst
, ins
->src
[1]);
436 mark_node_class(ldst
, ins
->src
[2]);
440 mark_node_class(texr
, ins
->src
[0]);
441 mark_node_class(texr
, ins
->src
[1]);
442 mark_node_class(texr
, ins
->src
[2]);
443 mark_node_class(texw
, ins
->dest
);
448 /* Pass #2 is lowering now that we've analyzed all the classes.
449 * Conceptually, if an index is only marked for a single type of use,
450 * there is nothing to lower. If it is marked for different uses, we
451 * split up based on the number of types of uses. To do so, we divide
452 * into N distinct classes of use (where N>1 by definition), emit N-1
453 * moves from the index to copies of the index, and finally rewrite N-1
454 * of the types of uses to use the corresponding move */
456 unsigned spill_idx
= ctx
->temp_count
;
458 for (unsigned i
= 0; i
< ctx
->temp_count
; ++i
) {
459 bool is_alur
= BITSET_TEST(alur
, i
);
460 bool is_aluw
= BITSET_TEST(aluw
, i
);
461 bool is_brar
= BITSET_TEST(brar
, i
);
462 bool is_ldst
= BITSET_TEST(ldst
, i
);
463 bool is_texr
= BITSET_TEST(texr
, i
);
464 bool is_texw
= BITSET_TEST(texw
, i
);
466 /* Analyse to check how many distinct uses there are. ALU ops
467 * (alur) can read the results of the texture pipeline (texw)
468 * but not ldst or texr. Load/store ops (ldst) cannot read
469 * anything but load/store inputs. Texture pipeline cannot read
470 * anything but texture inputs. TODO: Simplify. */
473 (is_alur
&& (is_ldst
|| is_texr
)) ||
474 (is_ldst
&& (is_alur
|| is_texr
|| is_texw
)) ||
475 (is_texr
&& (is_alur
|| is_ldst
|| is_texw
)) ||
476 (is_texw
&& (is_aluw
|| is_ldst
|| is_texr
)) ||
477 (is_brar
&& is_texw
);
482 /* Use the index as-is as the work copy. Emit copies for
485 unsigned classes
[] = { TAG_LOAD_STORE_4
, TAG_TEXTURE_4
, TAG_TEXTURE_4
, TAG_ALU_4
};
486 bool collisions
[] = { is_ldst
, is_texr
, is_texw
&& is_aluw
, is_brar
};
488 for (unsigned j
= 0; j
< ARRAY_SIZE(collisions
); ++j
) {
489 if (!collisions
[j
]) continue;
491 /* When the hazard is from reading, we move and rewrite
492 * sources (typical case). When it's from writing, we
493 * flip the move and rewrite destinations (obscure,
494 * only from control flow -- impossible in SSA) */
496 bool hazard_write
= (j
== 2);
498 unsigned idx
= spill_idx
++;
500 midgard_instruction m
= hazard_write
?
501 v_mov(idx
, blank_alu_src
, i
) :
502 v_mov(i
, blank_alu_src
, idx
);
504 /* Insert move before each read/write, depending on the
505 * hazard we're trying to account for */
507 mir_foreach_instr_global_safe(ctx
, pre_use
) {
508 if (pre_use
->type
!= classes
[j
])
512 if (pre_use
->dest
!= i
)
515 if (!mir_has_arg(pre_use
, i
))
520 midgard_instruction
*use
= mir_next_op(pre_use
);
522 mir_insert_instruction_before(ctx
, use
, m
);
523 mir_rewrite_index_dst_single(pre_use
, i
, idx
);
526 m
= v_mov(i
, blank_alu_src
, idx
);
527 m
.mask
= mir_mask_of_read_components(pre_use
, i
);
528 mir_insert_instruction_before(ctx
, pre_use
, m
);
529 mir_rewrite_index_src_single(pre_use
, i
, idx
);
544 mir_compute_interference(
545 compiler_context
*ctx
,
548 /* First, we need liveness information to be computed per block */
549 mir_compute_liveness(ctx
);
551 /* Now that every block has live_in/live_out computed, we can determine
552 * interference by walking each block linearly. Take live_out at the
553 * end of each block and walk the block backwards. */
555 mir_foreach_block(ctx
, blk
) {
556 uint8_t *live
= calloc(ctx
->temp_count
, 1);
558 mir_foreach_successor(blk
, succ
) {
559 for (unsigned i
= 0; i
< ctx
->temp_count
; ++i
)
560 live
[i
] |= succ
->live_in
[i
];
563 mir_foreach_instr_in_block_rev(blk
, ins
) {
564 /* Mark all registers live after the instruction as
565 * interfering with the destination */
567 unsigned dest
= ins
->dest
;
569 if (dest
< ctx
->temp_count
) {
570 for (unsigned i
= 0; i
< ctx
->temp_count
; ++i
)
572 ra_add_node_interference(g
, dest
, i
);
576 mir_liveness_ins_update(live
, ins
, ctx
->temp_count
);
582 mir_foreach_block(ctx
, blk
) {
588 /* This routine performs the actual register allocation. It should be succeeded
589 * by install_registers */
592 allocate_registers(compiler_context
*ctx
, bool *spilled
)
594 /* The number of vec4 work registers available depends on when the
595 * uniforms start, so compute that first */
596 int work_count
= 16 - MAX2((ctx
->uniform_cutoff
- 8), 0);
597 unsigned *classes
= NULL
;
598 struct ra_regs
*regs
= get_register_set(ctx
->screen
, work_count
, &classes
);
600 assert(regs
!= NULL
);
601 assert(classes
!= NULL
);
603 /* No register allocation to do with no SSA */
605 if (!ctx
->temp_count
)
608 /* Let's actually do register allocation */
609 int nodes
= ctx
->temp_count
;
610 struct ra_graph
*g
= ra_alloc_interference_graph(regs
, nodes
);
612 /* Register class (as known to the Mesa register allocator) is actually
613 * the product of both semantic class (work, load/store, texture..) and
614 * size (vec2/vec3..). First, we'll go through and determine the
615 * minimum size needed to hold values */
617 unsigned *found_class
= calloc(sizeof(unsigned), ctx
->temp_count
);
619 mir_foreach_instr_global(ctx
, ins
) {
620 if (ins
->dest
>= SSA_FIXED_MINIMUM
) continue;
622 /* 0 for x, 1 for xy, 2 for xyz, 3 for xyzw */
623 int class = util_logbase2(ins
->mask
);
625 /* Use the largest class if there's ambiguity, this
626 * handles partial writes */
628 int dest
= ins
->dest
;
629 found_class
[dest
] = MAX2(found_class
[dest
], class);
632 /* Next, we'll determine semantic class. We default to zero (work).
633 * But, if we're used with a special operation, that will force us to a
634 * particular class. Each node must be assigned to exactly one class; a
635 * prepass before RA should have lowered what-would-have-been
636 * multiclass nodes into a series of moves to break it up into multiple
639 mir_foreach_instr_global(ctx
, ins
) {
640 /* Check if this operation imposes any classes */
642 if (ins
->type
== TAG_LOAD_STORE_4
) {
643 bool force_vec4_only
= OP_IS_VEC4_ONLY(ins
->load_store
.op
);
645 set_class(found_class
, ins
->src
[0], REG_CLASS_LDST
);
646 set_class(found_class
, ins
->src
[1], REG_CLASS_LDST
);
647 set_class(found_class
, ins
->src
[2], REG_CLASS_LDST
);
649 if (force_vec4_only
) {
650 force_vec4(found_class
, ins
->dest
);
651 force_vec4(found_class
, ins
->src
[0]);
652 force_vec4(found_class
, ins
->src
[1]);
653 force_vec4(found_class
, ins
->src
[2]);
655 } else if (ins
->type
== TAG_TEXTURE_4
) {
656 set_class(found_class
, ins
->dest
, REG_CLASS_TEXW
);
657 set_class(found_class
, ins
->src
[0], REG_CLASS_TEXR
);
658 set_class(found_class
, ins
->src
[1], REG_CLASS_TEXR
);
659 set_class(found_class
, ins
->src
[2], REG_CLASS_TEXR
);
663 /* Check that the semantics of the class are respected */
664 mir_foreach_instr_global(ctx
, ins
) {
665 assert(check_write_class(found_class
, ins
->type
, ins
->dest
));
666 assert(check_read_class(found_class
, ins
->type
, ins
->src
[0]));
667 assert(check_read_class(found_class
, ins
->type
, ins
->src
[1]));
668 assert(check_read_class(found_class
, ins
->type
, ins
->src
[2]));
671 /* Mark writeout to r0 */
672 mir_foreach_instr_global(ctx
, ins
) {
673 if (ins
->compact_branch
&& ins
->writeout
)
674 set_class(found_class
, ins
->src
[0], REG_CLASS_FRAGC
);
677 for (unsigned i
= 0; i
< ctx
->temp_count
; ++i
) {
678 unsigned class = found_class
[i
];
679 ra_set_node_class(g
, i
, classes
[class]);
682 mir_compute_interference(ctx
, g
);
684 if (!ra_allocate(g
)) {
690 /* Whether we were successful or not, report the graph so we can
691 * compute spill nodes */
696 /* Once registers have been decided via register allocation
697 * (allocate_registers), we need to rewrite the MIR to use registers instead of
701 install_registers_instr(
702 compiler_context
*ctx
,
704 midgard_instruction
*ins
)
711 if (ins
->compact_branch
)
714 struct phys_reg src1
= index_to_reg(ctx
, g
, ins
->src
[0]);
715 struct phys_reg src2
= index_to_reg(ctx
, g
, ins
->src
[1]);
716 struct phys_reg dest
= index_to_reg(ctx
, g
, ins
->dest
);
718 unsigned uncomposed_mask
= ins
->mask
;
719 ins
->mask
= compose_writemask(uncomposed_mask
, dest
);
721 /* Adjust the dest mask if necessary. Mostly this is a no-op
722 * but it matters for dot products */
723 dest
.mask
= effective_writemask(&ins
->alu
, ins
->mask
);
725 midgard_vector_alu_src mod1
=
726 vector_alu_from_unsigned(ins
->alu
.src1
);
727 mod1
.swizzle
= compose_swizzle(mod1
.swizzle
, uncomposed_mask
, src1
, dest
);
728 ins
->alu
.src1
= vector_alu_srco_unsigned(mod1
);
730 ins
->registers
.src1_reg
= src1
.reg
;
732 ins
->registers
.src2_imm
= ins
->has_inline_constant
;
734 if (ins
->has_inline_constant
) {
735 /* Encode inline 16-bit constant. See disassembler for
736 * where the algorithm is from */
738 ins
->registers
.src2_reg
= ins
->inline_constant
>> 11;
740 int lower_11
= ins
->inline_constant
& ((1 << 12) - 1);
741 uint16_t imm
= ((lower_11
>> 8) & 0x7) |
742 ((lower_11
& 0xFF) << 3);
744 ins
->alu
.src2
= imm
<< 2;
746 midgard_vector_alu_src mod2
=
747 vector_alu_from_unsigned(ins
->alu
.src2
);
748 mod2
.swizzle
= compose_swizzle(
749 mod2
.swizzle
, uncomposed_mask
, src2
, dest
);
750 ins
->alu
.src2
= vector_alu_srco_unsigned(mod2
);
752 ins
->registers
.src2_reg
= src2
.reg
;
755 ins
->registers
.out_reg
= dest
.reg
;
759 case TAG_LOAD_STORE_4
: {
760 /* Which physical register we read off depends on
761 * whether we are loading or storing -- think about the
762 * logical dataflow */
764 bool encodes_src
= OP_IS_STORE(ins
->load_store
.op
);
767 struct phys_reg src
= index_to_reg(ctx
, g
, ins
->src
[0]);
768 assert(src
.reg
== 26 || src
.reg
== 27);
770 ins
->load_store
.reg
= src
.reg
- 26;
772 unsigned shift
= __builtin_ctz(src
.mask
);
773 unsigned adjusted_mask
= src
.mask
>> shift
;
774 assert(((adjusted_mask
+ 1) & adjusted_mask
) == 0);
776 unsigned new_swizzle
= 0;
777 for (unsigned q
= 0; q
< 4; ++q
) {
778 unsigned c
= (ins
->load_store
.swizzle
>> (2*q
)) & 3;
779 new_swizzle
|= (c
+ shift
) << (2*q
);
782 ins
->load_store
.swizzle
= compose_swizzle(
783 new_swizzle
, src
.mask
,
784 default_phys_reg(0), src
);
786 struct phys_reg src
= index_to_reg(ctx
, g
, ins
->dest
);
788 ins
->load_store
.reg
= src
.reg
;
790 ins
->load_store
.swizzle
= compose_swizzle(
791 ins
->load_store
.swizzle
, 0xF,
792 default_phys_reg(0), src
);
794 ins
->mask
= compose_writemask(
798 /* We also follow up by actual arguments */
801 encodes_src
? ins
->src
[1] : ins
->src
[0];
804 encodes_src
? ins
->src
[2] : ins
->src
[1];
807 struct phys_reg src
= index_to_reg(ctx
, g
, src2
);
808 unsigned component
= __builtin_ctz(src
.mask
);
809 ins
->load_store
.arg_1
|= midgard_ldst_reg(src
.reg
, component
);
813 struct phys_reg src
= index_to_reg(ctx
, g
, src3
);
814 unsigned component
= __builtin_ctz(src
.mask
);
815 ins
->load_store
.arg_2
|= midgard_ldst_reg(src
.reg
, component
);
821 case TAG_TEXTURE_4
: {
822 /* Grab RA results */
823 struct phys_reg dest
= index_to_reg(ctx
, g
, ins
->dest
);
824 struct phys_reg coord
= index_to_reg(ctx
, g
, ins
->src
[0]);
825 struct phys_reg lod
= index_to_reg(ctx
, g
, ins
->src
[1]);
827 assert(dest
.reg
== 28 || dest
.reg
== 29);
828 assert(coord
.reg
== 28 || coord
.reg
== 29);
830 /* First, install the texture coordinate */
831 ins
->texture
.in_reg_full
= 1;
832 ins
->texture
.in_reg_upper
= 0;
833 ins
->texture
.in_reg_select
= coord
.reg
- 28;
834 ins
->texture
.in_reg_swizzle
=
835 compose_swizzle(ins
->texture
.in_reg_swizzle
, 0xF, coord
, dest
);
837 /* Next, install the destination */
838 ins
->texture
.out_full
= 1;
839 ins
->texture
.out_upper
= 0;
840 ins
->texture
.out_reg_select
= dest
.reg
- 28;
841 ins
->texture
.swizzle
=
842 compose_swizzle(ins
->texture
.swizzle
, dest
.mask
, dest
, dest
);
844 compose_writemask(ins
->mask
, dest
);
846 /* If there is a register LOD/bias, use it */
847 if (ins
->src
[1] != ~0) {
848 midgard_tex_register_select sel
= {
851 .component
= lod
.swizzle
& 3,
855 memcpy(&packed
, &sel
, sizeof(packed
));
856 ins
->texture
.bias
= packed
;
868 install_registers(compiler_context
*ctx
, struct ra_graph
*g
)
870 mir_foreach_instr_global(ctx
, ins
)
871 install_registers_instr(ctx
, g
, ins
);