2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
3 * Copyright (C) 2019 Collabora, Ltd.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 #include "midgard_ops.h"
27 #include "util/register_allocate.h"
28 #include "util/u_math.h"
30 /* For work registers, we can subdivide in various ways. So we create
31 * classes for the various sizes and conflict accordingly, keeping in
32 * mind that physical registers are divided along 128-bit boundaries.
33 * The important part is that 128-bit boundaries are not crossed.
35 * For each 128-bit register, we can subdivide to 32-bits 10 ways
42 * For each 64-bit register, we can subdivide similarly to 16-bit
43 * (TODO: half-float RA, not that we support fp16 yet)
46 #define WORK_STRIDE 10
48 /* We have overlapping register classes for special registers, handled via
55 /* Prepacked masks/swizzles for virtual register types */
56 static unsigned reg_type_to_mask
[WORK_STRIDE
] = {
58 0x7, 0x7 << 1, /* xyz */
59 0x3, 0x3 << 1, 0x3 << 2, /* xy */
60 0x1, 0x1 << 1, 0x1 << 2, 0x1 << 3 /* x */
63 static unsigned reg_type_to_swizzle
[WORK_STRIDE
] = {
64 SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
66 SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
67 SWIZZLE(COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
, COMPONENT_W
),
69 SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
70 SWIZZLE(COMPONENT_Y
, COMPONENT_Z
, COMPONENT_Z
, COMPONENT_W
),
71 SWIZZLE(COMPONENT_Z
, COMPONENT_W
, COMPONENT_Z
, COMPONENT_W
),
73 SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
74 SWIZZLE(COMPONENT_Y
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
75 SWIZZLE(COMPONENT_Z
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
76 SWIZZLE(COMPONENT_W
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
85 /* Given the mask/swizzle of both the register and the original source,
86 * compose to find the actual mask/swizzle to give the hardware */
89 compose_writemask(unsigned mask
, struct phys_reg reg
)
91 /* Note: the reg mask is guaranteed to be contiguous. So we shift
92 * into the X place, compose via a simple AND, and shift back */
94 unsigned shift
= __builtin_ctz(reg
.mask
);
95 return ((reg
.mask
>> shift
) & mask
) << shift
;
99 compose_swizzle(unsigned swizzle
, unsigned mask
,
100 struct phys_reg reg
, struct phys_reg dst
)
102 unsigned out
= pan_compose_swizzle(swizzle
, reg
.swizzle
);
104 /* Based on the register mask, we need to adjust over. E.g if we're
105 * writing to yz, a base swizzle of xy__ becomes _xy_. Save the
106 * original first component (x). But to prevent duplicate shifting
107 * (only applies to ALU -- mask param is set to xyzw out on L/S to
108 * prevent changes), we have to account for the shift inherent to the
109 * original writemask */
111 unsigned rep
= out
& 0x3;
112 unsigned shift
= __builtin_ctz(dst
.mask
) - __builtin_ctz(mask
);
113 unsigned shifted
= out
<< (2*shift
);
115 /* ..but we fill in the gaps so it appears to replicate */
117 for (unsigned s
= 0; s
< shift
; ++s
)
118 shifted
|= rep
<< (2*s
);
123 /* Helper to return the default phys_reg for a given register */
125 static struct phys_reg
126 default_phys_reg(int reg
)
128 struct phys_reg r
= {
130 .mask
= 0xF, /* xyzw */
131 .swizzle
= 0xE4 /* xyzw */
137 /* Determine which physical register, swizzle, and mask a virtual
138 * register corresponds to */
140 static struct phys_reg
141 index_to_reg(compiler_context
*ctx
, struct ra_graph
*g
, int reg
)
143 /* Check for special cases */
144 if (reg
>= SSA_FIXED_MINIMUM
)
145 return default_phys_reg(SSA_REG_FROM_FIXED(reg
));
146 else if ((reg
< 0) || !g
)
147 return default_phys_reg(REGISTER_UNUSED
);
149 /* Special cases aside, we pick the underlying register */
150 int virt
= ra_get_node_reg(g
, reg
);
152 /* Divide out the register and classification */
153 int phys
= virt
/ WORK_STRIDE
;
154 int type
= virt
% WORK_STRIDE
;
156 /* Apply shadow registers */
158 if (phys
>= SHADOW_R27
&& phys
<= SHADOW_R29
)
159 phys
+= 27 - SHADOW_R27
;
161 struct phys_reg r
= {
163 .mask
= reg_type_to_mask
[type
],
164 .swizzle
= reg_type_to_swizzle
[type
]
167 /* Report that we actually use this register, and return it */
170 ctx
->work_registers
= MAX2(ctx
->work_registers
, phys
);
175 /* This routine creates a register set. Should be called infrequently since
176 * it's slow and can be cached. For legibility, variables are named in terms of
177 * work registers, although it is also used to create the register set for
178 * special register allocation */
181 add_shadow_conflicts (struct ra_regs
*regs
, unsigned base
, unsigned shadow
)
183 for (unsigned a
= 0; a
< WORK_STRIDE
; ++a
) {
184 unsigned reg_a
= (WORK_STRIDE
* base
) + a
;
186 for (unsigned b
= 0; b
< WORK_STRIDE
; ++b
) {
187 unsigned reg_b
= (WORK_STRIDE
* shadow
) + b
;
189 ra_add_reg_conflict(regs
, reg_a
, reg_b
);
190 ra_add_reg_conflict(regs
, reg_b
, reg_a
);
195 static struct ra_regs
*
196 create_register_set(unsigned work_count
, unsigned *classes
)
198 int virtual_count
= 32 * WORK_STRIDE
;
200 /* First, initialize the RA */
201 struct ra_regs
*regs
= ra_alloc_reg_set(NULL
, virtual_count
, true);
203 for (unsigned c
= 0; c
< NR_REG_CLASSES
; ++c
) {
204 int work_vec4
= ra_alloc_reg_class(regs
);
205 int work_vec3
= ra_alloc_reg_class(regs
);
206 int work_vec2
= ra_alloc_reg_class(regs
);
207 int work_vec1
= ra_alloc_reg_class(regs
);
209 classes
[4*c
+ 0] = work_vec1
;
210 classes
[4*c
+ 1] = work_vec2
;
211 classes
[4*c
+ 2] = work_vec3
;
212 classes
[4*c
+ 3] = work_vec4
;
214 /* Special register classes have other register counts */
216 (c
== REG_CLASS_WORK
) ? work_count
:
217 (c
== REG_CLASS_LDST27
) ? 1 : 2;
219 /* We arbitraily pick r17 (RA unused) as the shadow for r27 */
221 (c
== REG_CLASS_LDST
) ? 26 :
222 (c
== REG_CLASS_LDST27
) ? SHADOW_R27
:
223 (c
== REG_CLASS_TEXR
) ? 28 :
224 (c
== REG_CLASS_TEXW
) ? SHADOW_R28
:
227 /* Add the full set of work registers */
228 for (unsigned i
= first_reg
; i
< (first_reg
+ count
); ++i
) {
229 int base
= WORK_STRIDE
* i
;
231 /* Build a full set of subdivisions */
232 ra_class_add_reg(regs
, work_vec4
, base
);
233 ra_class_add_reg(regs
, work_vec3
, base
+ 1);
234 ra_class_add_reg(regs
, work_vec3
, base
+ 2);
235 ra_class_add_reg(regs
, work_vec2
, base
+ 3);
236 ra_class_add_reg(regs
, work_vec2
, base
+ 4);
237 ra_class_add_reg(regs
, work_vec2
, base
+ 5);
238 ra_class_add_reg(regs
, work_vec1
, base
+ 6);
239 ra_class_add_reg(regs
, work_vec1
, base
+ 7);
240 ra_class_add_reg(regs
, work_vec1
, base
+ 8);
241 ra_class_add_reg(regs
, work_vec1
, base
+ 9);
243 for (unsigned a
= 0; a
< 10; ++a
) {
244 unsigned mask1
= reg_type_to_mask
[a
];
246 for (unsigned b
= 0; b
< 10; ++b
) {
247 unsigned mask2
= reg_type_to_mask
[b
];
250 ra_add_reg_conflict(regs
,
258 /* We have duplicate classes */
259 add_shadow_conflicts(regs
, 27, SHADOW_R27
);
260 add_shadow_conflicts(regs
, 28, SHADOW_R28
);
261 add_shadow_conflicts(regs
, 29, SHADOW_R29
);
263 /* We're done setting up */
264 ra_set_finalize(regs
, NULL
);
269 /* This routine gets a precomputed register set off the screen if it's able, or
270 * otherwise it computes one on the fly */
272 static struct ra_regs
*
273 get_register_set(struct midgard_screen
*screen
, unsigned work_count
, unsigned **classes
)
276 assert(work_count
>= 8);
277 assert(work_count
<= 16);
280 unsigned index
= work_count
- 8;
282 /* Find the reg set */
283 struct ra_regs
*cached
= screen
->regs
[index
];
286 assert(screen
->reg_classes
[index
]);
287 *classes
= screen
->reg_classes
[index
];
291 /* Otherwise, create one */
292 struct ra_regs
*created
= create_register_set(work_count
, screen
->reg_classes
[index
]);
294 /* Cache it and use it */
295 screen
->regs
[index
] = created
;
297 *classes
= screen
->reg_classes
[index
];
301 /* Assign a (special) class, ensuring that it is compatible with whatever class
305 set_class(unsigned *classes
, unsigned node
, unsigned class)
307 /* Check that we're even a node */
308 if ((node
< 0) || (node
>= SSA_FIXED_MINIMUM
))
311 /* First 4 are work, next 4 are load/store.. */
312 unsigned current_class
= classes
[node
] >> 2;
315 if (class == current_class
)
319 if ((current_class
== REG_CLASS_LDST27
) && (class == REG_CLASS_LDST
))
322 /* If we're changing, we must not have already assigned a special class
325 bool compat
= current_class
== REG_CLASS_WORK
;
326 compat
|= (current_class
== REG_CLASS_LDST
) && (class == REG_CLASS_LDST27
);
330 classes
[node
] &= 0x3;
331 classes
[node
] |= (class << 2);
335 force_vec4(unsigned *classes
, unsigned node
)
337 if ((node
< 0) || (node
>= SSA_FIXED_MINIMUM
))
341 classes
[node
] |= 0x3;
344 /* Special register classes impose special constraints on who can read their
345 * values, so check that */
348 check_read_class(unsigned *classes
, unsigned tag
, unsigned node
)
350 /* Non-nodes are implicitly ok */
351 if ((node
< 0) || (node
>= SSA_FIXED_MINIMUM
))
354 unsigned current_class
= classes
[node
] >> 2;
356 switch (current_class
) {
358 case REG_CLASS_LDST27
:
359 return (tag
== TAG_LOAD_STORE_4
);
361 return (tag
== TAG_TEXTURE_4
);
363 return (tag
!= TAG_LOAD_STORE_4
);
365 return (tag
== TAG_ALU_4
);
367 unreachable("Invalid class");
372 check_write_class(unsigned *classes
, unsigned tag
, unsigned node
)
374 /* Non-nodes are implicitly ok */
375 if ((node
< 0) || (node
>= SSA_FIXED_MINIMUM
))
378 unsigned current_class
= classes
[node
] >> 2;
380 switch (current_class
) {
384 return (tag
== TAG_TEXTURE_4
);
386 case REG_CLASS_LDST27
:
388 return (tag
== TAG_ALU_4
) || (tag
== TAG_LOAD_STORE_4
);
390 unreachable("Invalid class");
394 /* Prepass before RA to ensure special class restrictions are met. The idea is
395 * to create a bit field of types of instructions that read a particular index.
396 * Later, we'll add moves as appropriate and rewrite to specialize by type. */
399 mark_node_class (unsigned *bitfield
, unsigned node
)
401 if ((node
>= 0) && (node
< SSA_FIXED_MINIMUM
))
402 BITSET_SET(bitfield
, node
);
406 mir_lower_special_reads(compiler_context
*ctx
)
408 size_t sz
= BITSET_WORDS(ctx
->temp_count
) * sizeof(BITSET_WORD
);
410 /* Bitfields for the various types of registers we could have */
412 unsigned *alur
= calloc(sz
, 1);
413 unsigned *aluw
= calloc(sz
, 1);
414 unsigned *ldst
= calloc(sz
, 1);
415 unsigned *texr
= calloc(sz
, 1);
416 unsigned *texw
= calloc(sz
, 1);
418 /* Pass #1 is analysis, a linear scan to fill out the bitfields */
420 mir_foreach_instr_global(ctx
, ins
) {
423 mark_node_class(aluw
, ins
->ssa_args
.dest
);
424 mark_node_class(alur
, ins
->ssa_args
.src0
);
426 if (!ins
->ssa_args
.inline_constant
)
427 mark_node_class(alur
, ins
->ssa_args
.src1
);
430 case TAG_LOAD_STORE_4
:
431 mark_node_class(ldst
, ins
->ssa_args
.src0
);
432 mark_node_class(ldst
, ins
->ssa_args
.src1
);
435 mark_node_class(texr
, ins
->ssa_args
.src0
);
436 mark_node_class(texr
, ins
->ssa_args
.src1
);
437 mark_node_class(texw
, ins
->ssa_args
.dest
);
442 /* Pass #2 is lowering now that we've analyzed all the classes.
443 * Conceptually, if an index is only marked for a single type of use,
444 * there is nothing to lower. If it is marked for different uses, we
445 * split up based on the number of types of uses. To do so, we divide
446 * into N distinct classes of use (where N>1 by definition), emit N-1
447 * moves from the index to copies of the index, and finally rewrite N-1
448 * of the types of uses to use the corresponding move */
450 unsigned spill_idx
= ctx
->temp_count
;
452 for (unsigned i
= 0; i
< ctx
->temp_count
; ++i
) {
453 bool is_alur
= BITSET_TEST(alur
, i
);
454 bool is_aluw
= BITSET_TEST(aluw
, i
);
455 bool is_ldst
= BITSET_TEST(ldst
, i
);
456 bool is_texr
= BITSET_TEST(texr
, i
);
457 bool is_texw
= BITSET_TEST(texw
, i
);
459 /* Analyse to check how many distinct uses there are. ALU ops
460 * (alur) can read the results of the texture pipeline (texw)
461 * but not ldst or texr. Load/store ops (ldst) cannot read
462 * anything but load/store inputs. Texture pipeline cannot read
463 * anything but texture inputs. TODO: Simplify. */
466 (is_alur
&& (is_ldst
|| is_texr
)) ||
467 (is_ldst
&& (is_alur
|| is_texr
|| is_texw
)) ||
468 (is_texr
&& (is_alur
|| is_ldst
|| is_texw
)) ||
469 (is_texw
&& (is_aluw
|| is_ldst
|| is_texr
));
474 /* Use the index as-is as the work copy. Emit copies for
477 unsigned classes
[] = { TAG_LOAD_STORE_4
, TAG_TEXTURE_4
, TAG_TEXTURE_4
};
478 bool collisions
[] = { is_ldst
, is_texr
, is_texw
&& is_aluw
};
480 for (unsigned j
= 0; j
< ARRAY_SIZE(collisions
); ++j
) {
481 if (!collisions
[j
]) continue;
483 /* When the hazard is from reading, we move and rewrite
484 * sources (typical case). When it's from writing, we
485 * flip the move and rewrite destinations (obscure,
486 * only from control flow -- impossible in SSA) */
488 bool hazard_write
= (j
== 2);
490 unsigned idx
= spill_idx
++;
492 midgard_instruction m
= hazard_write
?
493 v_mov(idx
, blank_alu_src
, i
) :
494 v_mov(i
, blank_alu_src
, idx
);
496 /* Insert move after each write */
497 mir_foreach_instr_global_safe(ctx
, pre_use
) {
498 if (pre_use
->ssa_args
.dest
!= i
)
501 /* If the hazard is writing, we need to
502 * specific insert moves for the contentious
503 * class. If the hazard is reading, we insert
504 * moves whenever it is written */
506 if (hazard_write
&& pre_use
->type
!= classes
[j
])
509 midgard_instruction
*use
= mir_next_op(pre_use
);
511 mir_insert_instruction_before(use
, m
);
516 mir_rewrite_index_dst_tag(ctx
, i
, idx
, classes
[j
]);
518 mir_rewrite_index_src_tag(ctx
, i
, idx
, classes
[j
]);
529 /* This routine performs the actual register allocation. It should be succeeded
530 * by install_registers */
533 allocate_registers(compiler_context
*ctx
, bool *spilled
)
535 /* The number of vec4 work registers available depends on when the
536 * uniforms start, so compute that first */
537 int work_count
= 16 - MAX2((ctx
->uniform_cutoff
- 8), 0);
538 unsigned *classes
= NULL
;
539 struct ra_regs
*regs
= get_register_set(ctx
->screen
, work_count
, &classes
);
541 assert(regs
!= NULL
);
542 assert(classes
!= NULL
);
544 /* No register allocation to do with no SSA */
546 if (!ctx
->temp_count
)
549 /* Let's actually do register allocation */
550 int nodes
= ctx
->temp_count
;
551 struct ra_graph
*g
= ra_alloc_interference_graph(regs
, nodes
);
553 /* Register class (as known to the Mesa register allocator) is actually
554 * the product of both semantic class (work, load/store, texture..) and
555 * size (vec2/vec3..). First, we'll go through and determine the
556 * minimum size needed to hold values */
558 unsigned *found_class
= calloc(sizeof(unsigned), ctx
->temp_count
);
560 mir_foreach_instr_global(ctx
, ins
) {
561 if (ins
->ssa_args
.dest
< 0) continue;
562 if (ins
->ssa_args
.dest
>= SSA_FIXED_MINIMUM
) continue;
564 /* 0 for x, 1 for xy, 2 for xyz, 3 for xyzw */
565 int class = util_logbase2(ins
->mask
);
567 /* Use the largest class if there's ambiguity, this
568 * handles partial writes */
570 int dest
= ins
->ssa_args
.dest
;
571 found_class
[dest
] = MAX2(found_class
[dest
], class);
574 /* Next, we'll determine semantic class. We default to zero (work).
575 * But, if we're used with a special operation, that will force us to a
576 * particular class. Each node must be assigned to exactly one class; a
577 * prepass before RA should have lowered what-would-have-been
578 * multiclass nodes into a series of moves to break it up into multiple
581 mir_foreach_instr_global(ctx
, ins
) {
582 /* Check if this operation imposes any classes */
584 if (ins
->type
== TAG_LOAD_STORE_4
) {
585 bool force_r27
= OP_IS_R27_ONLY(ins
->load_store
.op
);
586 unsigned class = force_r27
? REG_CLASS_LDST27
: REG_CLASS_LDST
;
588 set_class(found_class
, ins
->ssa_args
.src0
, class);
589 set_class(found_class
, ins
->ssa_args
.src1
, class);
592 force_vec4(found_class
, ins
->ssa_args
.dest
);
593 force_vec4(found_class
, ins
->ssa_args
.src0
);
594 force_vec4(found_class
, ins
->ssa_args
.src1
);
596 } else if (ins
->type
== TAG_TEXTURE_4
) {
597 set_class(found_class
, ins
->ssa_args
.dest
, REG_CLASS_TEXW
);
598 set_class(found_class
, ins
->ssa_args
.src0
, REG_CLASS_TEXR
);
599 set_class(found_class
, ins
->ssa_args
.src1
, REG_CLASS_TEXR
);
603 /* Check that the semantics of the class are respected */
604 mir_foreach_instr_global(ctx
, ins
) {
605 assert(check_write_class(found_class
, ins
->type
, ins
->ssa_args
.dest
));
606 assert(check_read_class(found_class
, ins
->type
, ins
->ssa_args
.src0
));
608 if (!ins
->ssa_args
.inline_constant
)
609 assert(check_read_class(found_class
, ins
->type
, ins
->ssa_args
.src1
));
612 for (unsigned i
= 0; i
< ctx
->temp_count
; ++i
) {
613 unsigned class = found_class
[i
];
614 ra_set_node_class(g
, i
, classes
[class]);
617 /* Determine liveness */
619 int *live_start
= malloc(nodes
* sizeof(int));
620 int *live_end
= malloc(nodes
* sizeof(int));
622 /* Initialize as non-existent */
624 for (int i
= 0; i
< nodes
; ++i
) {
625 live_start
[i
] = live_end
[i
] = -1;
630 mir_foreach_block(ctx
, block
) {
631 mir_foreach_instr_in_block(block
, ins
) {
632 if (ins
->ssa_args
.dest
< SSA_FIXED_MINIMUM
) {
633 /* If this destination is not yet live, it is
634 * now since we just wrote it */
636 int dest
= ins
->ssa_args
.dest
;
638 if (dest
>= 0 && live_start
[dest
] == -1)
639 live_start
[dest
] = d
;
642 /* Since we just used a source, the source might be
643 * dead now. Scan the rest of the block for
644 * invocations, and if there are none, the source dies
648 ins
->ssa_args
.src0
, ins
->ssa_args
.src1
651 for (int src
= 0; src
< 2; ++src
) {
652 int s
= sources
[src
];
654 if (ins
->ssa_args
.inline_constant
&& src
== 1)
659 if (s
>= SSA_FIXED_MINIMUM
) continue;
661 if (!mir_is_live_after(ctx
, block
, ins
, s
)) {
670 /* If a node still hasn't been killed, kill it now */
672 for (int i
= 0; i
< nodes
; ++i
) {
673 /* live_start == -1 most likely indicates a pinned output */
675 if (live_end
[i
] == -1)
679 /* Setup interference between nodes that are live at the same time */
681 for (int i
= 0; i
< nodes
; ++i
) {
682 for (int j
= i
+ 1; j
< nodes
; ++j
) {
683 bool j_overlaps_i
= live_start
[j
] < live_end
[i
];
684 bool i_overlaps_j
= live_end
[j
] < live_start
[i
];
686 if (i_overlaps_j
|| j_overlaps_i
)
687 ra_add_node_interference(g
, i
, j
);
695 if (!ra_allocate(g
)) {
701 /* Whether we were successful or not, report the graph so we can
702 * compute spill nodes */
707 /* Once registers have been decided via register allocation
708 * (allocate_registers), we need to rewrite the MIR to use registers instead of
712 install_registers_instr(
713 compiler_context
*ctx
,
715 midgard_instruction
*ins
)
717 ssa_args args
= ins
->ssa_args
;
721 int adjusted_src
= args
.inline_constant
? -1 : args
.src1
;
722 struct phys_reg src1
= index_to_reg(ctx
, g
, args
.src0
);
723 struct phys_reg src2
= index_to_reg(ctx
, g
, adjusted_src
);
724 struct phys_reg dest
= index_to_reg(ctx
, g
, args
.dest
);
726 unsigned uncomposed_mask
= ins
->mask
;
727 ins
->mask
= compose_writemask(uncomposed_mask
, dest
);
729 /* Adjust the dest mask if necessary. Mostly this is a no-op
730 * but it matters for dot products */
731 dest
.mask
= effective_writemask(&ins
->alu
, ins
->mask
);
733 midgard_vector_alu_src mod1
=
734 vector_alu_from_unsigned(ins
->alu
.src1
);
735 mod1
.swizzle
= compose_swizzle(mod1
.swizzle
, uncomposed_mask
, src1
, dest
);
736 ins
->alu
.src1
= vector_alu_srco_unsigned(mod1
);
738 ins
->registers
.src1_reg
= src1
.reg
;
740 ins
->registers
.src2_imm
= args
.inline_constant
;
742 if (args
.inline_constant
) {
743 /* Encode inline 16-bit constant. See disassembler for
744 * where the algorithm is from */
746 ins
->registers
.src2_reg
= ins
->inline_constant
>> 11;
748 int lower_11
= ins
->inline_constant
& ((1 << 12) - 1);
749 uint16_t imm
= ((lower_11
>> 8) & 0x7) |
750 ((lower_11
& 0xFF) << 3);
752 ins
->alu
.src2
= imm
<< 2;
754 midgard_vector_alu_src mod2
=
755 vector_alu_from_unsigned(ins
->alu
.src2
);
756 mod2
.swizzle
= compose_swizzle(
757 mod2
.swizzle
, uncomposed_mask
, src2
, dest
);
758 ins
->alu
.src2
= vector_alu_srco_unsigned(mod2
);
760 ins
->registers
.src2_reg
= src2
.reg
;
763 ins
->registers
.out_reg
= dest
.reg
;
767 case TAG_LOAD_STORE_4
: {
768 bool fixed
= args
.src0
>= SSA_FIXED_MINIMUM
;
770 if (OP_IS_STORE_R26(ins
->load_store
.op
) && fixed
) {
771 ins
->load_store
.reg
= SSA_REG_FROM_FIXED(args
.src0
);
772 } else if (OP_IS_STORE_VARY(ins
->load_store
.op
)) {
773 struct phys_reg src
= index_to_reg(ctx
, g
, args
.src0
);
774 assert(src
.reg
== 26 || src
.reg
== 27);
776 ins
->load_store
.reg
= src
.reg
- 26;
778 /* TODO: swizzle/mask */
780 /* Which physical register we read off depends on
781 * whether we are loading or storing -- think about the
782 * logical dataflow */
785 OP_IS_STORE(ins
->load_store
.op
) &&
786 ins
->load_store
.op
!= midgard_op_st_cubemap_coords
;
788 unsigned r
= encodes_src
?
789 args
.src0
: args
.dest
;
791 struct phys_reg src
= index_to_reg(ctx
, g
, r
);
793 ins
->load_store
.reg
= src
.reg
;
795 ins
->load_store
.swizzle
= compose_swizzle(
796 ins
->load_store
.swizzle
, 0xF,
797 default_phys_reg(0), src
);
799 ins
->mask
= compose_writemask(
806 case TAG_TEXTURE_4
: {
807 /* Grab RA results */
808 struct phys_reg dest
= index_to_reg(ctx
, g
, args
.dest
);
809 struct phys_reg coord
= index_to_reg(ctx
, g
, args
.src0
);
810 struct phys_reg lod
= index_to_reg(ctx
, g
, args
.src1
);
812 assert(dest
.reg
== 28 || dest
.reg
== 29);
813 assert(coord
.reg
== 28 || coord
.reg
== 29);
815 /* First, install the texture coordinate */
816 ins
->texture
.in_reg_full
= 1;
817 ins
->texture
.in_reg_upper
= 0;
818 ins
->texture
.in_reg_select
= coord
.reg
- 28;
819 ins
->texture
.in_reg_swizzle
=
820 compose_swizzle(ins
->texture
.in_reg_swizzle
, 0xF, coord
, dest
);
822 /* Next, install the destination */
823 ins
->texture
.out_full
= 1;
824 ins
->texture
.out_upper
= 0;
825 ins
->texture
.out_reg_select
= dest
.reg
- 28;
826 ins
->texture
.swizzle
=
827 compose_swizzle(ins
->texture
.swizzle
, dest
.mask
, dest
, dest
);
829 compose_writemask(ins
->mask
, dest
);
831 /* If there is a register LOD/bias, use it */
832 if (args
.src1
> -1) {
833 midgard_tex_register_select sel
= {
836 .component
= lod
.swizzle
& 3,
840 memcpy(&packed
, &sel
, sizeof(packed
));
841 ins
->texture
.bias
= packed
;
853 install_registers(compiler_context
*ctx
, struct ra_graph
*g
)
855 mir_foreach_block(ctx
, block
) {
856 mir_foreach_instr_in_block(block
, ins
) {
857 install_registers_instr(ctx
, g
, ins
);