2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
3 * Copyright (C) 2019 Collabora, Ltd.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 #include "midgard_ops.h"
27 #include "util/register_allocate.h"
28 #include "util/u_math.h"
29 #include "util/u_memory.h"
31 /* For work registers, we can subdivide in various ways. So we create
32 * classes for the various sizes and conflict accordingly, keeping in
33 * mind that physical registers are divided along 128-bit boundaries.
34 * The important part is that 128-bit boundaries are not crossed.
36 * For each 128-bit register, we can subdivide to 32-bits 10 ways
43 * For each 64-bit register, we can subdivide similarly to 16-bit
44 * (TODO: half-float RA, not that we support fp16 yet)
47 #define WORK_STRIDE 10
49 /* We have overlapping register classes for special registers, handled via
56 /* Prepacked masks/swizzles for virtual register types */
57 static unsigned reg_type_to_mask
[WORK_STRIDE
] = {
59 0x7, 0x7 << 1, /* xyz */
60 0x3, 0x3 << 1, 0x3 << 2, /* xy */
61 0x1, 0x1 << 1, 0x1 << 2, 0x1 << 3 /* x */
64 static unsigned reg_type_to_swizzle
[WORK_STRIDE
] = {
65 SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
67 SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
68 SWIZZLE(COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
, COMPONENT_W
),
70 SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
71 SWIZZLE(COMPONENT_Y
, COMPONENT_Z
, COMPONENT_Z
, COMPONENT_W
),
72 SWIZZLE(COMPONENT_Z
, COMPONENT_W
, COMPONENT_Z
, COMPONENT_W
),
74 SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
75 SWIZZLE(COMPONENT_Y
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
76 SWIZZLE(COMPONENT_Z
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
77 SWIZZLE(COMPONENT_W
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
86 /* Given the mask/swizzle of both the register and the original source,
87 * compose to find the actual mask/swizzle to give the hardware */
90 compose_writemask(unsigned mask
, struct phys_reg reg
)
92 /* Note: the reg mask is guaranteed to be contiguous. So we shift
93 * into the X place, compose via a simple AND, and shift back */
95 unsigned shift
= __builtin_ctz(reg
.mask
);
96 return ((reg
.mask
>> shift
) & mask
) << shift
;
100 compose_swizzle(unsigned swizzle
, unsigned mask
,
101 struct phys_reg reg
, struct phys_reg dst
)
103 unsigned out
= pan_compose_swizzle(swizzle
, reg
.swizzle
);
105 /* Based on the register mask, we need to adjust over. E.g if we're
106 * writing to yz, a base swizzle of xy__ becomes _xy_. Save the
107 * original first component (x). But to prevent duplicate shifting
108 * (only applies to ALU -- mask param is set to xyzw out on L/S to
109 * prevent changes), we have to account for the shift inherent to the
110 * original writemask */
112 unsigned rep
= out
& 0x3;
113 unsigned shift
= __builtin_ctz(dst
.mask
) - __builtin_ctz(mask
);
114 unsigned shifted
= out
<< (2*shift
);
116 /* ..but we fill in the gaps so it appears to replicate */
118 for (unsigned s
= 0; s
< shift
; ++s
)
119 shifted
|= rep
<< (2*s
);
124 /* Helper to return the default phys_reg for a given register */
126 static struct phys_reg
127 default_phys_reg(int reg
)
129 struct phys_reg r
= {
131 .mask
= 0xF, /* xyzw */
132 .swizzle
= 0xE4 /* xyzw */
138 /* Determine which physical register, swizzle, and mask a virtual
139 * register corresponds to */
141 static struct phys_reg
142 index_to_reg(compiler_context
*ctx
, struct ra_graph
*g
, unsigned reg
)
144 /* Check for special cases */
146 return default_phys_reg(REGISTER_UNUSED
);
147 else if (reg
>= SSA_FIXED_MINIMUM
)
148 return default_phys_reg(SSA_REG_FROM_FIXED(reg
));
150 return default_phys_reg(REGISTER_UNUSED
);
152 /* Special cases aside, we pick the underlying register */
153 int virt
= ra_get_node_reg(g
, reg
);
155 /* Divide out the register and classification */
156 int phys
= virt
/ WORK_STRIDE
;
157 int type
= virt
% WORK_STRIDE
;
159 /* Apply shadow registers */
161 if (phys
>= SHADOW_R28
&& phys
<= SHADOW_R29
)
162 phys
+= 28 - SHADOW_R28
;
163 else if (phys
== SHADOW_R0
)
166 struct phys_reg r
= {
168 .mask
= reg_type_to_mask
[type
],
169 .swizzle
= reg_type_to_swizzle
[type
]
172 /* Report that we actually use this register, and return it */
175 ctx
->work_registers
= MAX2(ctx
->work_registers
, phys
);
180 /* This routine creates a register set. Should be called infrequently since
181 * it's slow and can be cached. For legibility, variables are named in terms of
182 * work registers, although it is also used to create the register set for
183 * special register allocation */
186 add_shadow_conflicts (struct ra_regs
*regs
, unsigned base
, unsigned shadow
, unsigned shadow_count
)
188 for (unsigned a
= 0; a
< WORK_STRIDE
; ++a
) {
189 unsigned reg_a
= (WORK_STRIDE
* base
) + a
;
191 for (unsigned b
= 0; b
< shadow_count
; ++b
) {
192 unsigned reg_b
= (WORK_STRIDE
* shadow
) + b
;
194 ra_add_reg_conflict(regs
, reg_a
, reg_b
);
195 ra_add_reg_conflict(regs
, reg_b
, reg_a
);
200 static struct ra_regs
*
201 create_register_set(unsigned work_count
, unsigned *classes
)
203 int virtual_count
= 32 * WORK_STRIDE
;
205 /* First, initialize the RA */
206 struct ra_regs
*regs
= ra_alloc_reg_set(NULL
, virtual_count
, true);
208 for (unsigned c
= 0; c
< (NR_REG_CLASSES
- 1); ++c
) {
209 int work_vec4
= ra_alloc_reg_class(regs
);
210 int work_vec3
= ra_alloc_reg_class(regs
);
211 int work_vec2
= ra_alloc_reg_class(regs
);
212 int work_vec1
= ra_alloc_reg_class(regs
);
214 classes
[4*c
+ 0] = work_vec1
;
215 classes
[4*c
+ 1] = work_vec2
;
216 classes
[4*c
+ 2] = work_vec3
;
217 classes
[4*c
+ 3] = work_vec4
;
219 /* Special register classes have other register counts */
221 (c
== REG_CLASS_WORK
) ? work_count
: 2;
224 (c
== REG_CLASS_LDST
) ? 26 :
225 (c
== REG_CLASS_TEXR
) ? 28 :
226 (c
== REG_CLASS_TEXW
) ? SHADOW_R28
:
229 /* Add the full set of work registers */
230 for (unsigned i
= first_reg
; i
< (first_reg
+ count
); ++i
) {
231 int base
= WORK_STRIDE
* i
;
233 /* Build a full set of subdivisions */
234 ra_class_add_reg(regs
, work_vec4
, base
);
235 ra_class_add_reg(regs
, work_vec3
, base
+ 1);
236 ra_class_add_reg(regs
, work_vec3
, base
+ 2);
237 ra_class_add_reg(regs
, work_vec2
, base
+ 3);
238 ra_class_add_reg(regs
, work_vec2
, base
+ 4);
239 ra_class_add_reg(regs
, work_vec2
, base
+ 5);
240 ra_class_add_reg(regs
, work_vec1
, base
+ 6);
241 ra_class_add_reg(regs
, work_vec1
, base
+ 7);
242 ra_class_add_reg(regs
, work_vec1
, base
+ 8);
243 ra_class_add_reg(regs
, work_vec1
, base
+ 9);
245 for (unsigned a
= 0; a
< 10; ++a
) {
246 unsigned mask1
= reg_type_to_mask
[a
];
248 for (unsigned b
= 0; b
< 10; ++b
) {
249 unsigned mask2
= reg_type_to_mask
[b
];
252 ra_add_reg_conflict(regs
,
259 int fragc
= ra_alloc_reg_class(regs
);
261 classes
[4*REG_CLASS_FRAGC
+ 0] = fragc
;
262 classes
[4*REG_CLASS_FRAGC
+ 1] = fragc
;
263 classes
[4*REG_CLASS_FRAGC
+ 2] = fragc
;
264 classes
[4*REG_CLASS_FRAGC
+ 3] = fragc
;
265 ra_class_add_reg(regs
, fragc
, WORK_STRIDE
* SHADOW_R0
);
267 /* We have duplicate classes */
268 add_shadow_conflicts(regs
, 0, SHADOW_R0
, 1);
269 add_shadow_conflicts(regs
, 28, SHADOW_R28
, WORK_STRIDE
);
270 add_shadow_conflicts(regs
, 29, SHADOW_R29
, WORK_STRIDE
);
272 /* We're done setting up */
273 ra_set_finalize(regs
, NULL
);
278 /* This routine gets a precomputed register set off the screen if it's able, or
279 * otherwise it computes one on the fly */
281 static struct ra_regs
*
282 get_register_set(struct midgard_screen
*screen
, unsigned work_count
, unsigned **classes
)
285 assert(work_count
>= 8);
286 assert(work_count
<= 16);
289 unsigned index
= work_count
- 8;
291 /* Find the reg set */
292 struct ra_regs
*cached
= screen
->regs
[index
];
295 assert(screen
->reg_classes
[index
]);
296 *classes
= screen
->reg_classes
[index
];
300 /* Otherwise, create one */
301 struct ra_regs
*created
= create_register_set(work_count
, screen
->reg_classes
[index
]);
303 /* Cache it and use it */
304 screen
->regs
[index
] = created
;
306 *classes
= screen
->reg_classes
[index
];
310 /* Assign a (special) class, ensuring that it is compatible with whatever class
314 set_class(unsigned *classes
, unsigned node
, unsigned class)
316 /* Check that we're even a node */
317 if (node
>= SSA_FIXED_MINIMUM
)
320 /* First 4 are work, next 4 are load/store.. */
321 unsigned current_class
= classes
[node
] >> 2;
324 if (class == current_class
)
327 /* If we're changing, we haven't assigned a special class */
328 assert(current_class
== REG_CLASS_WORK
);
330 classes
[node
] &= 0x3;
331 classes
[node
] |= (class << 2);
335 force_vec4(unsigned *classes
, unsigned node
)
337 if (node
>= SSA_FIXED_MINIMUM
)
341 classes
[node
] |= 0x3;
344 /* Special register classes impose special constraints on who can read their
345 * values, so check that */
348 check_read_class(unsigned *classes
, unsigned tag
, unsigned node
)
350 /* Non-nodes are implicitly ok */
351 if (node
>= SSA_FIXED_MINIMUM
)
354 unsigned current_class
= classes
[node
] >> 2;
356 switch (current_class
) {
358 return (tag
== TAG_LOAD_STORE_4
);
360 return (tag
== TAG_TEXTURE_4
);
362 return (tag
!= TAG_LOAD_STORE_4
);
366 unreachable("Invalid class");
371 check_write_class(unsigned *classes
, unsigned tag
, unsigned node
)
373 /* Non-nodes are implicitly ok */
374 if (node
>= SSA_FIXED_MINIMUM
)
377 unsigned current_class
= classes
[node
] >> 2;
379 switch (current_class
) {
383 return (tag
== TAG_TEXTURE_4
);
386 return IS_ALU(tag
) || (tag
== TAG_LOAD_STORE_4
);
388 unreachable("Invalid class");
392 /* Prepass before RA to ensure special class restrictions are met. The idea is
393 * to create a bit field of types of instructions that read a particular index.
394 * Later, we'll add moves as appropriate and rewrite to specialize by type. */
397 mark_node_class (unsigned *bitfield
, unsigned node
)
399 if (node
< SSA_FIXED_MINIMUM
)
400 BITSET_SET(bitfield
, node
);
404 mir_lower_special_reads(compiler_context
*ctx
)
406 size_t sz
= BITSET_WORDS(ctx
->temp_count
) * sizeof(BITSET_WORD
);
408 /* Bitfields for the various types of registers we could have. aluw can
409 * be written by either ALU or load/store */
411 unsigned *alur
= calloc(sz
, 1);
412 unsigned *aluw
= calloc(sz
, 1);
413 unsigned *brar
= calloc(sz
, 1);
414 unsigned *ldst
= calloc(sz
, 1);
415 unsigned *texr
= calloc(sz
, 1);
416 unsigned *texw
= calloc(sz
, 1);
418 /* Pass #1 is analysis, a linear scan to fill out the bitfields */
420 mir_foreach_instr_global(ctx
, ins
) {
423 mark_node_class(aluw
, ins
->dest
);
424 mark_node_class(alur
, ins
->src
[0]);
425 mark_node_class(alur
, ins
->src
[1]);
426 mark_node_class(alur
, ins
->src
[2]);
428 if (ins
->compact_branch
&& ins
->writeout
)
429 mark_node_class(brar
, ins
->src
[0]);
433 case TAG_LOAD_STORE_4
:
434 mark_node_class(aluw
, ins
->dest
);
435 mark_node_class(ldst
, ins
->src
[0]);
436 mark_node_class(ldst
, ins
->src
[1]);
437 mark_node_class(ldst
, ins
->src
[2]);
441 mark_node_class(texr
, ins
->src
[0]);
442 mark_node_class(texr
, ins
->src
[1]);
443 mark_node_class(texr
, ins
->src
[2]);
444 mark_node_class(texw
, ins
->dest
);
449 /* Pass #2 is lowering now that we've analyzed all the classes.
450 * Conceptually, if an index is only marked for a single type of use,
451 * there is nothing to lower. If it is marked for different uses, we
452 * split up based on the number of types of uses. To do so, we divide
453 * into N distinct classes of use (where N>1 by definition), emit N-1
454 * moves from the index to copies of the index, and finally rewrite N-1
455 * of the types of uses to use the corresponding move */
457 unsigned spill_idx
= ctx
->temp_count
;
459 for (unsigned i
= 0; i
< ctx
->temp_count
; ++i
) {
460 bool is_alur
= BITSET_TEST(alur
, i
);
461 bool is_aluw
= BITSET_TEST(aluw
, i
);
462 bool is_brar
= BITSET_TEST(brar
, i
);
463 bool is_ldst
= BITSET_TEST(ldst
, i
);
464 bool is_texr
= BITSET_TEST(texr
, i
);
465 bool is_texw
= BITSET_TEST(texw
, i
);
467 /* Analyse to check how many distinct uses there are. ALU ops
468 * (alur) can read the results of the texture pipeline (texw)
469 * but not ldst or texr. Load/store ops (ldst) cannot read
470 * anything but load/store inputs. Texture pipeline cannot read
471 * anything but texture inputs. TODO: Simplify. */
474 (is_alur
&& (is_ldst
|| is_texr
)) ||
475 (is_ldst
&& (is_alur
|| is_texr
|| is_texw
)) ||
476 (is_texr
&& (is_alur
|| is_ldst
|| is_texw
)) ||
477 (is_texw
&& (is_aluw
|| is_ldst
|| is_texr
)) ||
478 (is_brar
&& is_texw
);
483 /* Use the index as-is as the work copy. Emit copies for
486 unsigned classes
[] = { TAG_LOAD_STORE_4
, TAG_TEXTURE_4
, TAG_TEXTURE_4
, TAG_ALU_4
};
487 bool collisions
[] = { is_ldst
, is_texr
, is_texw
&& is_aluw
, is_brar
};
489 for (unsigned j
= 0; j
< ARRAY_SIZE(collisions
); ++j
) {
490 if (!collisions
[j
]) continue;
492 /* When the hazard is from reading, we move and rewrite
493 * sources (typical case). When it's from writing, we
494 * flip the move and rewrite destinations (obscure,
495 * only from control flow -- impossible in SSA) */
497 bool hazard_write
= (j
== 2);
499 unsigned idx
= spill_idx
++;
501 midgard_instruction m
= hazard_write
?
502 v_mov(idx
, blank_alu_src
, i
) :
503 v_mov(i
, blank_alu_src
, idx
);
505 /* Insert move before each read/write, depending on the
506 * hazard we're trying to account for */
508 mir_foreach_instr_global_safe(ctx
, pre_use
) {
509 if (pre_use
->type
!= classes
[j
])
513 if (pre_use
->dest
!= i
)
516 if (!mir_has_arg(pre_use
, i
))
521 midgard_instruction
*use
= mir_next_op(pre_use
);
523 mir_insert_instruction_before(ctx
, use
, m
);
524 mir_rewrite_index_dst_single(pre_use
, i
, idx
);
527 m
= v_mov(i
, blank_alu_src
, idx
);
528 m
.mask
= mir_from_bytemask(mir_bytemask_of_read_components(pre_use
, i
), midgard_reg_mode_32
);
529 mir_insert_instruction_before(ctx
, pre_use
, m
);
530 mir_rewrite_index_src_single(pre_use
, i
, idx
);
545 mir_compute_interference(
546 compiler_context
*ctx
,
549 /* First, we need liveness information to be computed per block */
550 mir_compute_liveness(ctx
);
552 /* Now that every block has live_in/live_out computed, we can determine
553 * interference by walking each block linearly. Take live_out at the
554 * end of each block and walk the block backwards. */
556 mir_foreach_block(ctx
, blk
) {
557 uint16_t *live
= mem_dup(blk
->live_out
, ctx
->temp_count
* sizeof(uint16_t));
559 mir_foreach_instr_in_block_rev(blk
, ins
) {
560 /* Mark all registers live after the instruction as
561 * interfering with the destination */
563 unsigned dest
= ins
->dest
;
565 if (dest
< ctx
->temp_count
) {
566 for (unsigned i
= 0; i
< ctx
->temp_count
; ++i
)
568 ra_add_node_interference(g
, dest
, i
);
572 mir_liveness_ins_update(live
, ins
, ctx
->temp_count
);
579 /* This routine performs the actual register allocation. It should be succeeded
580 * by install_registers */
583 allocate_registers(compiler_context
*ctx
, bool *spilled
)
585 /* The number of vec4 work registers available depends on when the
586 * uniforms start, so compute that first */
587 int work_count
= 16 - MAX2((ctx
->uniform_cutoff
- 8), 0);
588 unsigned *classes
= NULL
;
589 struct ra_regs
*regs
= get_register_set(ctx
->screen
, work_count
, &classes
);
591 assert(regs
!= NULL
);
592 assert(classes
!= NULL
);
594 /* No register allocation to do with no SSA */
596 if (!ctx
->temp_count
)
599 /* Let's actually do register allocation */
600 int nodes
= ctx
->temp_count
;
601 struct ra_graph
*g
= ra_alloc_interference_graph(regs
, nodes
);
603 /* Register class (as known to the Mesa register allocator) is actually
604 * the product of both semantic class (work, load/store, texture..) and
605 * size (vec2/vec3..). First, we'll go through and determine the
606 * minimum size needed to hold values */
608 unsigned *found_class
= calloc(sizeof(unsigned), ctx
->temp_count
);
610 mir_foreach_instr_global(ctx
, ins
) {
611 if (ins
->dest
>= SSA_FIXED_MINIMUM
) continue;
613 /* 0 for x, 1 for xy, 2 for xyz, 3 for xyzw */
614 int class = util_logbase2(ins
->mask
);
616 /* Use the largest class if there's ambiguity, this
617 * handles partial writes */
619 int dest
= ins
->dest
;
620 found_class
[dest
] = MAX2(found_class
[dest
], class);
623 /* Next, we'll determine semantic class. We default to zero (work).
624 * But, if we're used with a special operation, that will force us to a
625 * particular class. Each node must be assigned to exactly one class; a
626 * prepass before RA should have lowered what-would-have-been
627 * multiclass nodes into a series of moves to break it up into multiple
630 mir_foreach_instr_global(ctx
, ins
) {
631 /* Check if this operation imposes any classes */
633 if (ins
->type
== TAG_LOAD_STORE_4
) {
634 bool force_vec4_only
= OP_IS_VEC4_ONLY(ins
->load_store
.op
);
636 set_class(found_class
, ins
->src
[0], REG_CLASS_LDST
);
637 set_class(found_class
, ins
->src
[1], REG_CLASS_LDST
);
638 set_class(found_class
, ins
->src
[2], REG_CLASS_LDST
);
640 if (force_vec4_only
) {
641 force_vec4(found_class
, ins
->dest
);
642 force_vec4(found_class
, ins
->src
[0]);
643 force_vec4(found_class
, ins
->src
[1]);
644 force_vec4(found_class
, ins
->src
[2]);
646 } else if (ins
->type
== TAG_TEXTURE_4
) {
647 set_class(found_class
, ins
->dest
, REG_CLASS_TEXW
);
648 set_class(found_class
, ins
->src
[0], REG_CLASS_TEXR
);
649 set_class(found_class
, ins
->src
[1], REG_CLASS_TEXR
);
650 set_class(found_class
, ins
->src
[2], REG_CLASS_TEXR
);
654 /* Check that the semantics of the class are respected */
655 mir_foreach_instr_global(ctx
, ins
) {
656 assert(check_write_class(found_class
, ins
->type
, ins
->dest
));
657 assert(check_read_class(found_class
, ins
->type
, ins
->src
[0]));
658 assert(check_read_class(found_class
, ins
->type
, ins
->src
[1]));
659 assert(check_read_class(found_class
, ins
->type
, ins
->src
[2]));
662 /* Mark writeout to r0 */
663 mir_foreach_instr_global(ctx
, ins
) {
664 if (ins
->compact_branch
&& ins
->writeout
)
665 set_class(found_class
, ins
->src
[0], REG_CLASS_FRAGC
);
668 for (unsigned i
= 0; i
< ctx
->temp_count
; ++i
) {
669 unsigned class = found_class
[i
];
670 ra_set_node_class(g
, i
, classes
[class]);
673 mir_compute_interference(ctx
, g
);
675 if (!ra_allocate(g
)) {
681 /* Whether we were successful or not, report the graph so we can
682 * compute spill nodes */
687 /* Once registers have been decided via register allocation
688 * (allocate_registers), we need to rewrite the MIR to use registers instead of
692 install_registers_instr(
693 compiler_context
*ctx
,
695 midgard_instruction
*ins
)
702 if (ins
->compact_branch
)
705 struct phys_reg src1
= index_to_reg(ctx
, g
, ins
->src
[0]);
706 struct phys_reg src2
= index_to_reg(ctx
, g
, ins
->src
[1]);
707 struct phys_reg dest
= index_to_reg(ctx
, g
, ins
->dest
);
709 unsigned uncomposed_mask
= ins
->mask
;
710 ins
->mask
= compose_writemask(uncomposed_mask
, dest
);
712 /* Adjust the dest mask if necessary. Mostly this is a no-op
713 * but it matters for dot products */
714 dest
.mask
= effective_writemask(&ins
->alu
, ins
->mask
);
716 midgard_vector_alu_src mod1
=
717 vector_alu_from_unsigned(ins
->alu
.src1
);
718 mod1
.swizzle
= compose_swizzle(mod1
.swizzle
, uncomposed_mask
, src1
, dest
);
719 ins
->alu
.src1
= vector_alu_srco_unsigned(mod1
);
721 ins
->registers
.src1_reg
= src1
.reg
;
723 ins
->registers
.src2_imm
= ins
->has_inline_constant
;
725 if (ins
->has_inline_constant
) {
726 /* Encode inline 16-bit constant. See disassembler for
727 * where the algorithm is from */
729 ins
->registers
.src2_reg
= ins
->inline_constant
>> 11;
731 int lower_11
= ins
->inline_constant
& ((1 << 12) - 1);
732 uint16_t imm
= ((lower_11
>> 8) & 0x7) |
733 ((lower_11
& 0xFF) << 3);
735 ins
->alu
.src2
= imm
<< 2;
737 midgard_vector_alu_src mod2
=
738 vector_alu_from_unsigned(ins
->alu
.src2
);
739 mod2
.swizzle
= compose_swizzle(
740 mod2
.swizzle
, uncomposed_mask
, src2
, dest
);
741 ins
->alu
.src2
= vector_alu_srco_unsigned(mod2
);
743 ins
->registers
.src2_reg
= src2
.reg
;
746 ins
->registers
.out_reg
= dest
.reg
;
750 case TAG_LOAD_STORE_4
: {
751 /* Which physical register we read off depends on
752 * whether we are loading or storing -- think about the
753 * logical dataflow */
755 bool encodes_src
= OP_IS_STORE(ins
->load_store
.op
);
758 struct phys_reg src
= index_to_reg(ctx
, g
, ins
->src
[0]);
759 assert(src
.reg
== 26 || src
.reg
== 27);
761 ins
->load_store
.reg
= src
.reg
- 26;
763 unsigned shift
= __builtin_ctz(src
.mask
);
764 unsigned adjusted_mask
= src
.mask
>> shift
;
765 assert(((adjusted_mask
+ 1) & adjusted_mask
) == 0);
767 unsigned new_swizzle
= 0;
768 for (unsigned q
= 0; q
< 4; ++q
) {
769 unsigned c
= (ins
->load_store
.swizzle
>> (2*q
)) & 3;
770 new_swizzle
|= (c
+ shift
) << (2*q
);
773 ins
->load_store
.swizzle
= compose_swizzle(
774 new_swizzle
, src
.mask
,
775 default_phys_reg(0), src
);
777 struct phys_reg src
= index_to_reg(ctx
, g
, ins
->dest
);
779 ins
->load_store
.reg
= src
.reg
;
781 ins
->load_store
.swizzle
= compose_swizzle(
782 ins
->load_store
.swizzle
, 0xF,
783 default_phys_reg(0), src
);
785 ins
->mask
= compose_writemask(
789 /* We also follow up by actual arguments */
792 encodes_src
? ins
->src
[1] : ins
->src
[0];
795 encodes_src
? ins
->src
[2] : ins
->src
[1];
798 struct phys_reg src
= index_to_reg(ctx
, g
, src2
);
799 unsigned component
= __builtin_ctz(src
.mask
);
800 ins
->load_store
.arg_1
|= midgard_ldst_reg(src
.reg
, component
);
804 struct phys_reg src
= index_to_reg(ctx
, g
, src3
);
805 unsigned component
= __builtin_ctz(src
.mask
);
806 ins
->load_store
.arg_2
|= midgard_ldst_reg(src
.reg
, component
);
812 case TAG_TEXTURE_4
: {
813 /* Grab RA results */
814 struct phys_reg dest
= index_to_reg(ctx
, g
, ins
->dest
);
815 struct phys_reg coord
= index_to_reg(ctx
, g
, ins
->src
[0]);
816 struct phys_reg lod
= index_to_reg(ctx
, g
, ins
->src
[1]);
818 assert(dest
.reg
== 28 || dest
.reg
== 29);
819 assert(coord
.reg
== 28 || coord
.reg
== 29);
821 /* First, install the texture coordinate */
822 ins
->texture
.in_reg_full
= 1;
823 ins
->texture
.in_reg_upper
= 0;
824 ins
->texture
.in_reg_select
= coord
.reg
- 28;
825 ins
->texture
.in_reg_swizzle
=
826 compose_swizzle(ins
->texture
.in_reg_swizzle
, 0xF, coord
, dest
);
828 /* Next, install the destination */
829 ins
->texture
.out_full
= 1;
830 ins
->texture
.out_upper
= 0;
831 ins
->texture
.out_reg_select
= dest
.reg
- 28;
832 ins
->texture
.swizzle
=
833 compose_swizzle(ins
->texture
.swizzle
, dest
.mask
, dest
, dest
);
835 compose_writemask(ins
->mask
, dest
);
837 /* If there is a register LOD/bias, use it */
838 if (ins
->src
[1] != ~0) {
839 midgard_tex_register_select sel
= {
842 .component
= lod
.swizzle
& 3,
846 memcpy(&packed
, &sel
, sizeof(packed
));
847 ins
->texture
.bias
= packed
;
859 install_registers(compiler_context
*ctx
, struct ra_graph
*g
)
861 mir_foreach_instr_global(ctx
, ins
)
862 install_registers_instr(ctx
, g
, ins
);