src/panfrost/midgard/midgard_ra_pipeline.c

   1 /*
   2  * Copyright (C) 2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
   3  * Copyright (C) 2019 Collabora, Ltd.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  */
  24
  25 #include "compiler.h"
  26
  27 /* Creates pipeline registers. This is a prepass run before the main register
  28  * allocator but after scheduling, once bundles are created. It works by
  29  * iterating the scheduled IR, checking if a value is ever used after the end
  30  * of the current bundle. If it is not, it is promoted to a bundle-specific
  31  * pipeline register.
  32  *
  33  * Pipeline registers are only written from the first two stages of the
  34  * pipeline (vmul/sadd) lasting the duration of the bundle only. There are two
  35  * 128-bit pipeline registers available (r24/r25). The upshot is that no actual
  36  * register allocation is needed; we can _always_ promote a value to a pipeline
  37  * register, liveness permitting. This greatly simplifies the logic of this
  38  * passing, negating the need for a proper RA like work registers.
  39  */
  40
  41 static bool
  42 mir_pipeline_ins(
  43         compiler_context *ctx,
  44         midgard_block *block,
  45         midgard_bundle *bundle, unsigned i,
  46         unsigned pipeline_count)
  47 {
  48         midgard_instruction *ins = bundle->instructions[i];
  49         unsigned dest = ins->dest;
  50
  51         /* We could be pipelining a register, so we need to make sure that all
  52          * of the components read in this bundle are written in this bundle,
  53          * and that no components are written before this bundle */
  54
  55         unsigned node = ins->dest;
  56         unsigned read_mask = 0;
  57
  58         /* Analyze the bundle for a read mask */
  59
  60         for (unsigned i = 0; i < bundle->instruction_count; ++i) {
  61                 midgard_instruction *q = bundle->instructions[i];
  62                 read_mask |= mir_mask_of_read_components(q, node);
  63
  64                 /* The fragment colour can't be pipelined (well, it is
  65                  * pipelined in r0, but this is a delicate dance with
  66                  * scheduling and RA, not for us to worry about) */
  67
  68                 if (q->compact_branch && q->writeout && mir_has_arg(q, node))
  69                         return false;
  70         }
  71
  72         /* Now analyze for a write mask */
  73         for (unsigned i = 0; i < bundle->instruction_count; ++i) {
  74                 midgard_instruction *q = bundle->instructions[i];
  75                 if (q->dest != node) continue;
  76
  77                 /* Remove the written mask from the read requirements */
  78                 read_mask &= ~q->mask;
  79         }
  80
  81         /* Check for leftovers */
  82         if (read_mask)
  83                 return false;
  84
  85         /* Now, check outside the bundle */
  86         midgard_instruction *start = bundle->instructions[0];
  87
  88         if (mir_is_written_before(ctx, start, node))
  89                 return false;
  90
  91         /* We want to know if we live after this bundle, so check if
  92          * we're live after the last instruction of the bundle */
  93
  94         midgard_instruction *end = bundle->instructions[
  95                                     bundle->instruction_count - 1];
  96
  97         if (mir_is_live_after(ctx, block, end, ins->dest))
  98                 return false;
  99
 100         /* We're only live in this bundle -- pipeline! */
 101
 102         mir_rewrite_index(ctx, dest, SSA_FIXED_REGISTER(24 + pipeline_count));
 103
 104         return true;
 105 }
 106
 107 void
 108 mir_create_pipeline_registers(compiler_context *ctx)
 109 {
 110         mir_foreach_block(ctx, block) {
 111                 mir_foreach_bundle_in_block(block, bundle) {
 112                         if (!mir_is_alu_bundle(bundle)) continue;
 113                         if (bundle->instruction_count < 2) continue;
 114
 115                         /* Only first 2 instructions could pipeline */
 116                         bool succ = mir_pipeline_ins(ctx, block, bundle, 0, 0);
 117                         mir_pipeline_ins(ctx, block, bundle, 1, succ);
 118                 }
 119         }
 120 }