2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 #include "midgard_ops.h"
26 #include "midgard_quirks.h"
27 #include "util/u_memory.h"
28 #include "util/u_math.h"
29 #include "util/half_float.h"
31 /* Scheduling for Midgard is complicated, to say the least. ALU instructions
32 * must be grouped into VLIW bundles according to following model:
35 * [VADD] [SMUL] [VLUT]
37 * A given instruction can execute on some subset of the units (or a few can
38 * execute on all). Instructions can be either vector or scalar; only scalar
39 * instructions can execute on SADD/SMUL units. Units on a given line execute
40 * in parallel. Subsequent lines execute separately and can pass results
41 * directly via pipeline registers r24/r25, bypassing the register file.
43 * A bundle can optionally have 128-bits of embedded constants, shared across
44 * all of the instructions within a bundle.
46 * Instructions consuming conditionals (branches and conditional selects)
47 * require their condition to be written into the conditional register (r31)
48 * within the same bundle they are consumed.
50 * Fragment writeout requires its argument to be written in full within the
51 * same bundle as the branch, with no hanging dependencies.
53 * Load/store instructions are also in bundles of simply two instructions, and
54 * texture instructions have no bundling.
56 * -------------------------------------------------------------------------
60 /* We create the dependency graph with per-byte granularity */
65 add_dependency(struct util_dynarray
*table
, unsigned index
, uint16_t mask
, midgard_instruction
**instructions
, unsigned child
)
67 for (unsigned i
= 0; i
< BYTE_COUNT
; ++i
) {
68 if (!(mask
& (1 << i
)))
71 struct util_dynarray
*parents
= &table
[(BYTE_COUNT
* index
) + i
];
73 util_dynarray_foreach(parents
, unsigned, parent
) {
74 BITSET_WORD
*dependents
= instructions
[*parent
]->dependents
;
76 /* Already have the dependency */
77 if (BITSET_TEST(dependents
, child
))
80 BITSET_SET(dependents
, child
);
81 instructions
[child
]->nr_dependencies
++;
87 mark_access(struct util_dynarray
*table
, unsigned index
, uint16_t mask
, unsigned parent
)
89 for (unsigned i
= 0; i
< BYTE_COUNT
; ++i
) {
90 if (!(mask
& (1 << i
)))
93 util_dynarray_append(&table
[(BYTE_COUNT
* index
) + i
], unsigned, parent
);
98 mir_create_dependency_graph(midgard_instruction
**instructions
, unsigned count
, unsigned node_count
)
100 size_t sz
= node_count
* BYTE_COUNT
;
102 struct util_dynarray
*last_read
= calloc(sizeof(struct util_dynarray
), sz
);
103 struct util_dynarray
*last_write
= calloc(sizeof(struct util_dynarray
), sz
);
105 for (unsigned i
= 0; i
< sz
; ++i
) {
106 util_dynarray_init(&last_read
[i
], NULL
);
107 util_dynarray_init(&last_write
[i
], NULL
);
110 /* Initialize dependency graph */
111 for (unsigned i
= 0; i
< count
; ++i
) {
112 instructions
[i
]->dependents
=
113 calloc(BITSET_WORDS(count
), sizeof(BITSET_WORD
));
115 instructions
[i
]->nr_dependencies
= 0;
118 /* Populate dependency graph */
119 for (signed i
= count
- 1; i
>= 0; --i
) {
120 if (instructions
[i
]->compact_branch
)
123 unsigned dest
= instructions
[i
]->dest
;
124 unsigned mask
= mir_bytemask(instructions
[i
]);
126 mir_foreach_src((*instructions
), s
) {
127 unsigned src
= instructions
[i
]->src
[s
];
129 if (src
< node_count
) {
130 unsigned readmask
= mir_bytemask_of_read_components(instructions
[i
], src
);
131 add_dependency(last_write
, src
, readmask
, instructions
, i
);
135 if (dest
< node_count
) {
136 add_dependency(last_read
, dest
, mask
, instructions
, i
);
137 add_dependency(last_write
, dest
, mask
, instructions
, i
);
138 mark_access(last_write
, dest
, mask
, i
);
141 mir_foreach_src((*instructions
), s
) {
142 unsigned src
= instructions
[i
]->src
[s
];
144 if (src
< node_count
) {
145 unsigned readmask
= mir_bytemask_of_read_components(instructions
[i
], src
);
146 mark_access(last_read
, src
, readmask
, i
);
151 /* If there is a branch, all instructions depend on it, as interblock
152 * execution must be purely in-order */
154 if (instructions
[count
- 1]->compact_branch
) {
155 BITSET_WORD
*dependents
= instructions
[count
- 1]->dependents
;
157 for (signed i
= count
- 2; i
>= 0; --i
) {
158 if (BITSET_TEST(dependents
, i
))
161 BITSET_SET(dependents
, i
);
162 instructions
[i
]->nr_dependencies
++;
166 /* Free the intermediate structures */
167 for (unsigned i
= 0; i
< sz
; ++i
) {
168 util_dynarray_fini(&last_read
[i
]);
169 util_dynarray_fini(&last_write
[i
]);
176 /* Does the mask cover more than a scalar? */
179 is_single_component_mask(unsigned mask
)
183 for (int c
= 0; c
< 8; ++c
) {
188 return components
== 1;
191 /* Helpers for scheudling */
194 mir_is_scalar(midgard_instruction
*ains
)
196 /* Do we try to use it as a vector op? */
197 if (!is_single_component_mask(ains
->mask
))
200 /* Otherwise, check mode hazards */
201 bool could_scalar
= true;
202 unsigned szd
= nir_alu_type_get_type_size(ains
->dest_type
);
203 unsigned sz0
= nir_alu_type_get_type_size(ains
->src_types
[0]);
204 unsigned sz1
= nir_alu_type_get_type_size(ains
->src_types
[1]);
206 /* Only 16/32-bit can run on a scalar unit */
207 could_scalar
&= (szd
== 16) || (szd
== 32);
209 if (ains
->src
[0] != ~0)
210 could_scalar
&= (sz0
== 16) || (sz0
== 32);
212 if (ains
->src
[1] != ~0)
213 could_scalar
&= (sz1
== 16) || (sz1
== 32);
215 if (midgard_is_integer_out_op(ains
->op
) && ains
->outmod
!= midgard_outmod_int_wrap
)
221 /* How many bytes does this ALU instruction add to the bundle? */
224 bytes_for_instruction(midgard_instruction
*ains
)
226 if (ains
->unit
& UNITS_ANY_VECTOR
)
227 return sizeof(midgard_reg_info
) + sizeof(midgard_vector_alu
);
228 else if (ains
->unit
== ALU_ENAB_BRANCH
)
229 return sizeof(midgard_branch_extended
);
230 else if (ains
->compact_branch
)
231 return sizeof(uint16_t);
233 return sizeof(midgard_reg_info
) + sizeof(midgard_scalar_alu
);
236 /* We would like to flatten the linked list of midgard_instructions in a bundle
237 * to an array of pointers on the heap for easy indexing */
239 static midgard_instruction
**
240 flatten_mir(midgard_block
*block
, unsigned *len
)
242 *len
= list_length(&block
->base
.instructions
);
247 midgard_instruction
**instructions
=
248 calloc(sizeof(midgard_instruction
*), *len
);
252 mir_foreach_instr_in_block(block
, ins
)
253 instructions
[i
++] = ins
;
258 /* The worklist is the set of instructions that can be scheduled now; that is,
259 * the set of instructions with no remaining dependencies */
262 mir_initialize_worklist(BITSET_WORD
*worklist
, midgard_instruction
**instructions
, unsigned count
)
264 for (unsigned i
= 0; i
< count
; ++i
) {
265 if (instructions
[i
]->nr_dependencies
== 0)
266 BITSET_SET(worklist
, i
);
270 /* Update the worklist after an instruction terminates. Remove its edges from
271 * the graph and if that causes any node to have no dependencies, add it to the
276 BITSET_WORD
*worklist
, unsigned count
,
277 midgard_instruction
**instructions
, midgard_instruction
*done
)
279 /* Sanity check: if no instruction terminated, there is nothing to do.
280 * If the instruction that terminated had dependencies, that makes no
281 * sense and means we messed up the worklist. Finally, as the purpose
282 * of this routine is to update dependents, we abort early if there are
283 * no dependents defined. */
288 assert(done
->nr_dependencies
== 0);
290 if (!done
->dependents
)
293 /* We have an instruction with dependents. Iterate each dependent to
294 * remove one dependency (`done`), adding dependents to the worklist
298 BITSET_FOREACH_SET(i
, done
->dependents
, count
) {
299 assert(instructions
[i
]->nr_dependencies
);
301 if (!(--instructions
[i
]->nr_dependencies
))
302 BITSET_SET(worklist
, i
);
305 free(done
->dependents
);
308 /* While scheduling, we need to choose instructions satisfying certain
309 * criteria. As we schedule backwards, we choose the *last* instruction in the
310 * worklist to simulate in-order scheduling. Chosen instructions must satisfy a
311 * given predicate. */
313 struct midgard_predicate
{
314 /* TAG or ~0 for dont-care */
317 /* True if we want to pop off the chosen instruction */
320 /* For ALU, choose only this unit */
323 /* State for bundle constants. constants is the actual constants
324 * for the bundle. constant_count is the number of bytes (up to
325 * 16) currently in use for constants. When picking in destructive
326 * mode, the constants array will be updated, and the instruction
327 * will be adjusted to index into the constants array */
329 midgard_constants
*constants
;
330 unsigned constant_mask
;
333 /* Exclude this destination (if not ~0) */
336 /* Don't schedule instructions consuming conditionals (since we already
337 * scheduled one). Excludes conditional branches and csel */
340 /* Require (or reject) a minimal mask and (if nonzero) given
341 * destination. Used for writeout optimizations */
347 /* Whether to not-care/only/never schedule imov/fmov instructions This
348 * allows non-move instructions to get priority on each unit */
351 /* For load/store: how many pipeline registers are in use? The two
352 * scheduled instructions cannot use more than the 256-bits of pipeline
353 * space available or RA will fail (as it would run out of pipeline
354 * registers and fail to spill without breaking the schedule) */
356 unsigned pipeline_count
;
360 mir_adjust_constant(midgard_instruction
*ins
, unsigned src
,
361 unsigned *bundle_constant_mask
,
362 unsigned *comp_mapping
,
363 uint8_t *bundle_constants
,
366 unsigned type_size
= nir_alu_type_get_type_size(ins
->src_types
[src
]) / 8;
367 unsigned type_shift
= util_logbase2(type_size
);
368 unsigned max_comp
= mir_components_for_type(ins
->src_types
[src
]);
369 unsigned comp_mask
= mir_from_bytemask(mir_round_bytemask_up(
370 mir_bytemask_of_read_components_index(ins
, src
),
373 unsigned type_mask
= (1 << type_size
) - 1;
375 /* Upper only makes sense for 16-bit */
376 if (type_size
!= 16 && upper
)
379 /* For 16-bit, we need to stay on either upper or lower halves to avoid
380 * disrupting the swizzle */
381 unsigned start
= upper
? 8 : 0;
382 unsigned length
= (type_size
== 2) ? 8 : 16;
384 for (unsigned comp
= 0; comp
< max_comp
; comp
++) {
385 if (!(comp_mask
& (1 << comp
)))
388 uint8_t *constantp
= ins
->constants
.u8
+ (type_size
* comp
);
389 unsigned best_reuse_bytes
= 0;
390 signed best_place
= -1;
393 for (i
= start
; i
< (start
+ length
); i
+= type_size
) {
394 unsigned reuse_bytes
= 0;
396 for (j
= 0; j
< type_size
; j
++) {
397 if (!(*bundle_constant_mask
& (1 << (i
+ j
))))
399 if (constantp
[j
] != bundle_constants
[i
+ j
])
401 if ((i
+ j
) > (start
+ length
))
407 /* Select the place where existing bytes can be
408 * reused so we leave empty slots to others
410 if (j
== type_size
&&
411 (reuse_bytes
> best_reuse_bytes
|| best_place
< 0)) {
412 best_reuse_bytes
= reuse_bytes
;
418 /* This component couldn't fit in the remaining constant slot,
419 * no need check the remaining components, bail out now
424 memcpy(&bundle_constants
[i
], constantp
, type_size
);
425 *bundle_constant_mask
|= type_mask
<< best_place
;
426 comp_mapping
[comp
] = best_place
>> type_shift
;
432 /* For an instruction that can fit, adjust it to fit and update the constants
433 * array, in destructive mode. Returns whether the fitting was successful. */
436 mir_adjust_constants(midgard_instruction
*ins
,
437 struct midgard_predicate
*pred
,
440 /* Blend constants dominate */
441 if (ins
->has_blend_constant
) {
442 if (pred
->constant_mask
)
444 else if (destructive
) {
445 pred
->blend_constant
= true;
446 pred
->constant_mask
= 0xffff;
451 /* No constant, nothing to adjust */
452 if (!ins
->has_constants
)
455 unsigned r_constant
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
456 unsigned bundle_constant_mask
= pred
->constant_mask
;
457 unsigned comp_mapping
[2][16] = { };
458 uint8_t bundle_constants
[16];
460 memcpy(bundle_constants
, pred
->constants
, 16);
462 /* Let's try to find a place for each active component of the constant
465 for (unsigned src
= 0; src
< 2; ++src
) {
466 if (ins
->src
[src
] != SSA_FIXED_REGISTER(REGISTER_CONSTANT
))
469 /* First, try lower half (or whole for !16) */
470 if (mir_adjust_constant(ins
, src
, &bundle_constant_mask
,
471 comp_mapping
[src
], bundle_constants
, false))
474 /* Next, try upper half */
475 if (mir_adjust_constant(ins
, src
, &bundle_constant_mask
,
476 comp_mapping
[src
], bundle_constants
, true))
483 /* If non-destructive, we're done */
487 /* Otherwise update the constant_mask and constant values */
488 pred
->constant_mask
= bundle_constant_mask
;
489 memcpy(pred
->constants
, bundle_constants
, 16);
491 /* Use comp_mapping as a swizzle */
492 mir_foreach_src(ins
, s
) {
493 if (ins
->src
[s
] == r_constant
)
494 mir_compose_swizzle(ins
->swizzle
[s
], comp_mapping
[s
], ins
->swizzle
[s
]);
500 /* Conservative estimate of the pipeline registers required for load/store */
503 mir_pipeline_count(midgard_instruction
*ins
)
505 unsigned bytecount
= 0;
507 mir_foreach_src(ins
, i
) {
508 /* Skip empty source */
509 if (ins
->src
[i
] == ~0) continue;
511 unsigned bytemask
= mir_bytemask_of_read_components_index(ins
, i
);
513 unsigned max
= util_logbase2(bytemask
) + 1;
517 return DIV_ROUND_UP(bytecount
, 16);
520 /* Matches FADD x, x with modifiers compatible. Since x + x = x * 2, for
521 * any x including of the form f(y) for some swizzle/abs/neg function f */
524 mir_is_add_2(midgard_instruction
*ins
)
526 if (ins
->op
!= midgard_alu_op_fadd
)
529 if (ins
->src
[0] != ins
->src
[1])
532 if (ins
->src_types
[0] != ins
->src_types
[1])
535 for (unsigned i
= 0; i
< MIR_VEC_COMPONENTS
; ++i
) {
536 if (ins
->swizzle
[0][i
] != ins
->swizzle
[1][i
])
540 if (ins
->src_abs
[0] != ins
->src_abs
[1])
543 if (ins
->src_neg
[0] != ins
->src_neg
[1])
550 mir_adjust_unit(midgard_instruction
*ins
, unsigned unit
)
552 /* FADD x, x = FMUL x, #2 */
553 if (mir_is_add_2(ins
) && (unit
& (UNITS_MUL
| UNIT_VLUT
))) {
554 ins
->op
= midgard_alu_op_fmul
;
557 ins
->src_abs
[1] = false;
558 ins
->src_neg
[1] = false;
560 ins
->has_inline_constant
= true;
561 ins
->inline_constant
= _mesa_float_to_half(2.0);
566 mir_has_unit(midgard_instruction
*ins
, unsigned unit
)
568 if (alu_opcode_props
[ins
->op
].props
& unit
)
571 /* FADD x, x can run on any adder or any multiplier */
572 if (mir_is_add_2(ins
))
578 /* Net change in liveness if an instruction were scheduled. Loosely based on
579 * ir3's scheduler. */
582 mir_live_effect(uint16_t *liveness
, midgard_instruction
*ins
, bool destructive
)
584 /* TODO: what if dest is used multiple times? */
587 if (ins
->dest
< SSA_FIXED_MINIMUM
) {
588 unsigned bytemask
= mir_bytemask(ins
);
589 bytemask
= util_next_power_of_two(bytemask
+ 1) - 1;
590 free_live
+= util_bitcount(liveness
[ins
->dest
] & bytemask
);
593 liveness
[ins
->dest
] &= ~bytemask
;
598 mir_foreach_src(ins
, s
) {
599 unsigned S
= ins
->src
[s
];
603 for (unsigned q
= 0; q
< s
; ++q
)
604 dupe
|= (ins
->src
[q
] == S
);
609 if (S
< SSA_FIXED_MINIMUM
) {
610 unsigned bytemask
= mir_bytemask_of_read_components(ins
, S
);
611 bytemask
= util_next_power_of_two(bytemask
+ 1) - 1;
613 /* Count only the new components */
614 new_live
+= util_bitcount(bytemask
& ~(liveness
[S
]));
617 liveness
[S
] |= bytemask
;
621 return new_live
- free_live
;
624 static midgard_instruction
*
625 mir_choose_instruction(
626 midgard_instruction
**instructions
,
628 BITSET_WORD
*worklist
, unsigned count
,
629 struct midgard_predicate
*predicate
)
631 /* Parse the predicate */
632 unsigned tag
= predicate
->tag
;
633 bool alu
= tag
== TAG_ALU_4
;
634 bool ldst
= tag
== TAG_LOAD_STORE_4
;
635 unsigned unit
= predicate
->unit
;
636 bool branch
= alu
&& (unit
== ALU_ENAB_BR_COMPACT
);
637 bool scalar
= (unit
!= ~0) && (unit
& UNITS_SCALAR
);
638 bool no_cond
= predicate
->no_cond
;
640 unsigned mask
= predicate
->mask
;
641 unsigned dest
= predicate
->dest
;
642 bool needs_dest
= mask
& 0xF;
644 /* Iterate to find the best instruction satisfying the predicate */
647 signed best_index
= -1;
648 signed best_effect
= INT_MAX
;
649 bool best_conditional
= false;
651 /* Enforce a simple metric limiting distance to keep down register
652 * pressure. TOOD: replace with liveness tracking for much better
655 unsigned max_active
= 0;
656 unsigned max_distance
= 36;
658 BITSET_FOREACH_SET(i
, worklist
, count
) {
659 max_active
= MAX2(max_active
, i
);
662 BITSET_FOREACH_SET(i
, worklist
, count
) {
663 bool is_move
= alu
&&
664 (instructions
[i
]->op
== midgard_alu_op_imov
||
665 instructions
[i
]->op
== midgard_alu_op_fmov
);
667 if ((max_active
- i
) >= max_distance
)
670 if (tag
!= ~0 && instructions
[i
]->type
!= tag
)
673 if (predicate
->exclude
!= ~0 && instructions
[i
]->dest
== predicate
->exclude
)
676 if (alu
&& !branch
&& !(mir_has_unit(instructions
[i
], unit
)))
679 /* 0: don't care, 1: no moves, 2: only moves */
680 if (predicate
->move_mode
&& ((predicate
->move_mode
- 1) != is_move
))
683 if (branch
&& !instructions
[i
]->compact_branch
)
686 if (alu
&& scalar
&& !mir_is_scalar(instructions
[i
]))
689 if (alu
&& !mir_adjust_constants(instructions
[i
], predicate
, false))
692 if (needs_dest
&& instructions
[i
]->dest
!= dest
)
695 if (mask
&& ((~instructions
[i
]->mask
) & mask
))
698 if (instructions
[i
]->mask
& predicate
->no_mask
)
701 if (ldst
&& mir_pipeline_count(instructions
[i
]) + predicate
->pipeline_count
> 2)
704 bool conditional
= alu
&& !branch
&& OP_IS_CSEL(instructions
[i
]->op
);
705 conditional
|= (branch
&& instructions
[i
]->branch
.conditional
);
707 if (conditional
&& no_cond
)
710 int effect
= mir_live_effect(liveness
, instructions
[i
], false);
712 if (effect
> best_effect
)
715 if (effect
== best_effect
&& (signed) i
< best_index
)
718 best_effect
= effect
;
720 best_conditional
= conditional
;
723 /* Did we find anything? */
728 /* If we found something, remove it from the worklist */
729 assert(best_index
< count
);
731 if (predicate
->destructive
) {
732 BITSET_CLEAR(worklist
, best_index
);
735 mir_adjust_constants(instructions
[best_index
], predicate
, true);
738 predicate
->pipeline_count
+= mir_pipeline_count(instructions
[best_index
]);
741 mir_adjust_unit(instructions
[best_index
], unit
);
743 /* Once we schedule a conditional, we can't again */
744 predicate
->no_cond
|= best_conditional
;
745 mir_live_effect(liveness
, instructions
[best_index
], true);
748 return instructions
[best_index
];
751 /* Still, we don't choose instructions in a vacuum. We need a way to choose the
752 * best bundle type (ALU, load/store, texture). Nondestructive. */
756 midgard_instruction
**instructions
,
758 BITSET_WORD
*worklist
, unsigned count
)
760 /* At the moment, our algorithm is very simple - use the bundle of the
761 * best instruction, regardless of what else could be scheduled
762 * alongside it. This is not optimal but it works okay for in-order */
764 struct midgard_predicate predicate
= {
766 .destructive
= false,
770 midgard_instruction
*chosen
= mir_choose_instruction(instructions
, liveness
, worklist
, count
, &predicate
);
778 /* We want to choose an ALU instruction filling a given unit */
780 mir_choose_alu(midgard_instruction
**slot
,
781 midgard_instruction
**instructions
,
783 BITSET_WORD
*worklist
, unsigned len
,
784 struct midgard_predicate
*predicate
,
787 /* Did we already schedule to this slot? */
791 /* Try to schedule something, if not */
792 predicate
->unit
= unit
;
793 *slot
= mir_choose_instruction(instructions
, liveness
, worklist
, len
, predicate
);
795 /* Store unit upon scheduling */
796 if (*slot
&& !((*slot
)->compact_branch
))
797 (*slot
)->unit
= unit
;
800 /* When we are scheduling a branch/csel, we need the consumed condition in the
801 * same block as a pipeline register. There are two options to enable this:
803 * - Move the conditional into the bundle. Preferred, but only works if the
804 * conditional is used only once and is from this block.
805 * - Copy the conditional.
807 * We search for the conditional. If it's in this block, single-use, and
808 * without embedded constants, we schedule it immediately. Otherwise, we
809 * schedule a move for it.
811 * mir_comparison_mobile is a helper to find the moveable condition.
815 mir_comparison_mobile(
816 compiler_context
*ctx
,
817 midgard_instruction
**instructions
,
818 struct midgard_predicate
*predicate
,
822 if (!mir_single_use(ctx
, cond
))
827 for (unsigned i
= 0; i
< count
; ++i
) {
828 if (instructions
[i
]->dest
!= cond
)
831 /* Must fit in an ALU bundle */
832 if (instructions
[i
]->type
!= TAG_ALU_4
)
835 /* If it would itself require a condition, that's recursive */
836 if (OP_IS_CSEL(instructions
[i
]->op
))
839 /* We'll need to rewrite to .w but that doesn't work for vector
840 * ops that don't replicate (ball/bany), so bail there */
842 if (GET_CHANNEL_COUNT(alu_opcode_props
[instructions
[i
]->op
].props
))
845 /* Ensure it will fit with constants */
847 if (!mir_adjust_constants(instructions
[i
], predicate
, false))
850 /* Ensure it is written only once */
858 /* Inject constants now that we are sure we want to */
860 mir_adjust_constants(instructions
[ret
], predicate
, true);
865 /* Using the information about the moveable conditional itself, we either pop
866 * that condition off the worklist for use now, or create a move to
867 * artificially schedule instead as a fallback */
869 static midgard_instruction
*
870 mir_schedule_comparison(
871 compiler_context
*ctx
,
872 midgard_instruction
**instructions
,
873 struct midgard_predicate
*predicate
,
874 BITSET_WORD
*worklist
, unsigned count
,
875 unsigned cond
, bool vector
, unsigned *swizzle
,
876 midgard_instruction
*user
)
878 /* TODO: swizzle when scheduling */
880 (!vector
&& (swizzle
[0] == 0)) ?
881 mir_comparison_mobile(ctx
, instructions
, predicate
, count
, cond
) : ~0;
883 /* If we can, schedule the condition immediately */
884 if ((comp_i
!= ~0) && BITSET_TEST(worklist
, comp_i
)) {
885 assert(comp_i
< count
);
886 BITSET_CLEAR(worklist
, comp_i
);
887 return instructions
[comp_i
];
890 /* Otherwise, we insert a move */
892 midgard_instruction mov
= v_mov(cond
, cond
);
893 mov
.mask
= vector
? 0xF : 0x1;
894 memcpy(mov
.swizzle
[1], swizzle
, sizeof(mov
.swizzle
[1]));
896 return mir_insert_instruction_before(ctx
, user
, mov
);
899 /* Most generally, we need instructions writing to r31 in the appropriate
902 static midgard_instruction
*
903 mir_schedule_condition(compiler_context
*ctx
,
904 struct midgard_predicate
*predicate
,
905 BITSET_WORD
*worklist
, unsigned count
,
906 midgard_instruction
**instructions
,
907 midgard_instruction
*last
)
909 /* For a branch, the condition is the only argument; for csel, third */
910 bool branch
= last
->compact_branch
;
911 unsigned condition_index
= branch
? 0 : 2;
913 /* csel_v is vector; otherwise, conditions are scalar */
914 bool vector
= !branch
&& OP_IS_CSEL_V(last
->op
);
916 /* Grab the conditional instruction */
918 midgard_instruction
*cond
= mir_schedule_comparison(
919 ctx
, instructions
, predicate
, worklist
, count
, last
->src
[condition_index
],
920 vector
, last
->swizzle
[2], last
);
922 /* We have exclusive reign over this (possibly move) conditional
923 * instruction. We can rewrite into a pipeline conditional register */
925 predicate
->exclude
= cond
->dest
;
926 cond
->dest
= SSA_FIXED_REGISTER(31);
929 cond
->mask
= (1 << COMPONENT_W
);
931 mir_foreach_src(cond
, s
) {
932 if (cond
->src
[s
] == ~0)
935 for (unsigned q
= 0; q
< 4; ++q
)
936 cond
->swizzle
[s
][q
+ COMPONENT_W
] = cond
->swizzle
[s
][q
];
940 /* Schedule the unit: csel is always in the latter pipeline, so a csel
941 * condition must be in the former pipeline stage (vmul/sadd),
942 * depending on scalar/vector of the instruction itself. A branch must
943 * be written from the latter pipeline stage and a branch condition is
944 * always scalar, so it is always in smul (exception: ball/bany, which
948 cond
->unit
= UNIT_SMUL
;
950 cond
->unit
= vector
? UNIT_VMUL
: UNIT_SADD
;
955 /* Schedules a single bundle of the given type */
957 static midgard_bundle
958 mir_schedule_texture(
959 midgard_instruction
**instructions
,
961 BITSET_WORD
*worklist
, unsigned len
,
964 struct midgard_predicate predicate
= {
965 .tag
= TAG_TEXTURE_4
,
970 midgard_instruction
*ins
=
971 mir_choose_instruction(instructions
, liveness
, worklist
, len
, &predicate
);
973 mir_update_worklist(worklist
, len
, instructions
, ins
);
975 struct midgard_bundle out
= {
976 .tag
= ins
->op
== TEXTURE_OP_BARRIER
?
977 TAG_TEXTURE_4_BARRIER
:
978 (ins
->op
== TEXTURE_OP_TEXEL_FETCH
) || is_vertex
?
979 TAG_TEXTURE_4_VTX
: TAG_TEXTURE_4
,
980 .instruction_count
= 1,
981 .instructions
= { ins
}
987 static midgard_bundle
989 midgard_instruction
**instructions
,
991 BITSET_WORD
*worklist
, unsigned len
)
993 struct midgard_predicate predicate
= {
994 .tag
= TAG_LOAD_STORE_4
,
999 /* Try to pick two load/store ops. Second not gauranteed to exist */
1001 midgard_instruction
*ins
=
1002 mir_choose_instruction(instructions
, liveness
, worklist
, len
, &predicate
);
1004 midgard_instruction
*pair
=
1005 mir_choose_instruction(instructions
, liveness
, worklist
, len
, &predicate
);
1007 struct midgard_bundle out
= {
1008 .tag
= TAG_LOAD_STORE_4
,
1009 .instruction_count
= pair
? 2 : 1,
1010 .instructions
= { ins
, pair
}
1013 /* We have to update the worklist atomically, since the two
1014 * instructions run concurrently (TODO: verify it's not pipelined) */
1016 mir_update_worklist(worklist
, len
, instructions
, ins
);
1017 mir_update_worklist(worklist
, len
, instructions
, pair
);
1023 mir_schedule_zs_write(
1024 compiler_context
*ctx
,
1025 struct midgard_predicate
*predicate
,
1026 midgard_instruction
**instructions
,
1028 BITSET_WORD
*worklist
, unsigned len
,
1029 midgard_instruction
*branch
,
1030 midgard_instruction
**smul
,
1031 midgard_instruction
**vadd
,
1032 midgard_instruction
**vlut
,
1035 bool success
= false;
1036 unsigned idx
= stencil
? 3 : 2;
1037 unsigned src
= (branch
->src
[0] == ~0) ? SSA_FIXED_REGISTER(1) : branch
->src
[idx
];
1039 predicate
->dest
= src
;
1040 predicate
->mask
= 0x1;
1042 midgard_instruction
**units
[] = { smul
, vadd
, vlut
};
1043 unsigned unit_names
[] = { UNIT_SMUL
, UNIT_VADD
, UNIT_VLUT
};
1045 for (unsigned i
= 0; i
< 3; ++i
) {
1049 predicate
->unit
= unit_names
[i
];
1050 midgard_instruction
*ins
=
1051 mir_choose_instruction(instructions
, liveness
, worklist
, len
, predicate
);
1054 ins
->unit
= unit_names
[i
];
1061 predicate
->dest
= predicate
->mask
= 0;
1066 midgard_instruction
*mov
= ralloc(ctx
, midgard_instruction
);
1067 *mov
= v_mov(src
, make_compiler_temp(ctx
));
1070 branch
->src
[idx
] = mov
->dest
;
1073 unsigned swizzle
= (branch
->src
[0] == ~0) ? COMPONENT_Y
: COMPONENT_X
;
1075 for (unsigned c
= 0; c
< 16; ++c
)
1076 mov
->swizzle
[1][c
] = swizzle
;
1079 for (unsigned i
= 0; i
< 3; ++i
) {
1080 if (!(*(units
[i
]))) {
1082 mov
->unit
= unit_names
[i
];
1087 unreachable("Could not schedule Z/S move to any unit");
1090 static midgard_bundle
1092 compiler_context
*ctx
,
1093 midgard_instruction
**instructions
,
1095 BITSET_WORD
*worklist
, unsigned len
)
1097 struct midgard_bundle bundle
= {};
1099 unsigned bytes_emitted
= sizeof(bundle
.control
);
1101 struct midgard_predicate predicate
= {
1103 .destructive
= true,
1105 .constants
= &bundle
.constants
1108 midgard_instruction
*vmul
= NULL
;
1109 midgard_instruction
*vadd
= NULL
;
1110 midgard_instruction
*vlut
= NULL
;
1111 midgard_instruction
*smul
= NULL
;
1112 midgard_instruction
*sadd
= NULL
;
1113 midgard_instruction
*branch
= NULL
;
1115 mir_choose_alu(&branch
, instructions
, liveness
, worklist
, len
, &predicate
, ALU_ENAB_BR_COMPACT
);
1116 mir_update_worklist(worklist
, len
, instructions
, branch
);
1117 unsigned writeout
= branch
? branch
->writeout
: 0;
1119 if (branch
&& branch
->branch
.conditional
) {
1120 midgard_instruction
*cond
= mir_schedule_condition(ctx
, &predicate
, worklist
, len
, instructions
, branch
);
1122 if (cond
->unit
== UNIT_VADD
)
1124 else if (cond
->unit
== UNIT_SMUL
)
1127 unreachable("Bad condition");
1130 /* If we have a render target reference, schedule a move for it. Since
1131 * this will be in sadd, we boost this to prevent scheduling csel into
1134 if (writeout
&& (branch
->constants
.u32
[0] || ctx
->is_blend
)) {
1135 sadd
= ralloc(ctx
, midgard_instruction
);
1136 *sadd
= v_mov(~0, make_compiler_temp(ctx
));
1137 sadd
->unit
= UNIT_SADD
;
1139 sadd
->has_inline_constant
= true;
1140 sadd
->inline_constant
= branch
->constants
.u32
[0];
1141 branch
->src
[1] = sadd
->dest
;
1142 branch
->src_types
[1] = sadd
->dest_type
;
1144 /* Mask off any conditionals. Could be optimized to just scalar
1145 * conditionals TODO */
1146 predicate
.no_cond
= true;
1151 bundle
.last_writeout
= branch
->last_writeout
;
1154 /* When MRT is in use, writeout loops require r1.w to be filled (with a
1155 * return address? by symmetry with Bifrost, etc), at least for blend
1156 * shaders to work properly. When MRT is not in use (including on SFBD
1157 * GPUs), this is not needed. Blend shaders themselves don't know if
1158 * they are paired with MRT or not so they always need this, at least
1161 if (writeout
&& (ctx
->is_blend
|| ctx
->writeout_branch
[1])) {
1162 vadd
= ralloc(ctx
, midgard_instruction
);
1163 *vadd
= v_mov(~0, make_compiler_temp(ctx
));
1165 if (!ctx
->is_blend
) {
1166 vadd
->op
= midgard_alu_op_iadd
;
1167 vadd
->src
[0] = SSA_FIXED_REGISTER(31);
1168 vadd
->src_types
[0] = nir_type_uint32
;
1170 for (unsigned c
= 0; c
< 16; ++c
)
1171 vadd
->swizzle
[0][c
] = COMPONENT_X
;
1173 vadd
->has_inline_constant
= true;
1174 vadd
->inline_constant
= 0;
1176 vadd
->src
[1] = SSA_FIXED_REGISTER(1);
1177 vadd
->src_types
[0] = nir_type_uint32
;
1179 for (unsigned c
= 0; c
< 16; ++c
)
1180 vadd
->swizzle
[1][c
] = COMPONENT_W
;
1183 vadd
->unit
= UNIT_VADD
;
1185 branch
->dest
= vadd
->dest
;
1186 branch
->dest_type
= vadd
->dest_type
;
1189 if (writeout
& PAN_WRITEOUT_Z
)
1190 mir_schedule_zs_write(ctx
, &predicate
, instructions
, liveness
, worklist
, len
, branch
, &smul
, &vadd
, &vlut
, false);
1192 if (writeout
& PAN_WRITEOUT_S
)
1193 mir_schedule_zs_write(ctx
, &predicate
, instructions
, liveness
, worklist
, len
, branch
, &smul
, &vadd
, &vlut
, true);
1195 mir_choose_alu(&smul
, instructions
, liveness
, worklist
, len
, &predicate
, UNIT_SMUL
);
1197 for (unsigned mode
= 1; mode
< 3; ++mode
) {
1198 predicate
.move_mode
= mode
;
1199 predicate
.no_mask
= writeout
? (1 << 3) : 0;
1200 mir_choose_alu(&vlut
, instructions
, liveness
, worklist
, len
, &predicate
, UNIT_VLUT
);
1201 predicate
.no_mask
= 0;
1202 mir_choose_alu(&vadd
, instructions
, liveness
, worklist
, len
, &predicate
, UNIT_VADD
);
1206 predicate
.move_mode
= 0;
1208 mir_update_worklist(worklist
, len
, instructions
, vlut
);
1209 mir_update_worklist(worklist
, len
, instructions
, vadd
);
1210 mir_update_worklist(worklist
, len
, instructions
, smul
);
1212 bool vadd_csel
= vadd
&& OP_IS_CSEL(vadd
->op
);
1213 bool smul_csel
= smul
&& OP_IS_CSEL(smul
->op
);
1215 if (vadd_csel
|| smul_csel
) {
1216 midgard_instruction
*ins
= vadd_csel
? vadd
: smul
;
1217 midgard_instruction
*cond
= mir_schedule_condition(ctx
, &predicate
, worklist
, len
, instructions
, ins
);
1219 if (cond
->unit
== UNIT_VMUL
)
1221 else if (cond
->unit
== UNIT_SADD
)
1224 unreachable("Bad condition");
1227 /* Stage 2, let's schedule sadd before vmul for writeout */
1228 mir_choose_alu(&sadd
, instructions
, liveness
, worklist
, len
, &predicate
, UNIT_SADD
);
1230 /* Check if writeout reads its own register */
1233 midgard_instruction
*stages
[] = { sadd
, vadd
, smul
, vlut
};
1234 unsigned src
= (branch
->src
[0] == ~0) ? SSA_FIXED_REGISTER(0) : branch
->src
[0];
1235 unsigned writeout_mask
= 0x0;
1236 bool bad_writeout
= false;
1238 for (unsigned i
= 0; i
< ARRAY_SIZE(stages
); ++i
) {
1242 if (stages
[i
]->dest
!= src
)
1245 writeout_mask
|= stages
[i
]->mask
;
1246 bad_writeout
|= mir_has_arg(stages
[i
], branch
->src
[0]);
1249 /* It's possible we'll be able to schedule something into vmul
1250 * to fill r0. Let's peak into the future, trying to schedule
1251 * vmul specially that way. */
1253 unsigned full_mask
= 0xF;
1255 if (!bad_writeout
&& writeout_mask
!= full_mask
) {
1256 predicate
.unit
= UNIT_VMUL
;
1257 predicate
.dest
= src
;
1258 predicate
.mask
= writeout_mask
^ full_mask
;
1260 struct midgard_instruction
*peaked
=
1261 mir_choose_instruction(instructions
, liveness
, worklist
, len
, &predicate
);
1265 vmul
->unit
= UNIT_VMUL
;
1266 writeout_mask
|= predicate
.mask
;
1267 assert(writeout_mask
== full_mask
);
1271 predicate
.dest
= predicate
.mask
= 0;
1274 /* Finally, add a move if necessary */
1275 if (bad_writeout
|| writeout_mask
!= full_mask
) {
1276 unsigned temp
= (branch
->src
[0] == ~0) ? SSA_FIXED_REGISTER(0) : make_compiler_temp(ctx
);
1278 vmul
= ralloc(ctx
, midgard_instruction
);
1279 *vmul
= v_mov(src
, temp
);
1280 vmul
->unit
= UNIT_VMUL
;
1281 vmul
->mask
= full_mask
^ writeout_mask
;
1283 /* Rewrite to use our temp */
1285 for (unsigned i
= 0; i
< ARRAY_SIZE(stages
); ++i
) {
1287 mir_rewrite_index_dst_single(stages
[i
], src
, temp
);
1290 mir_rewrite_index_src_single(branch
, src
, temp
);
1294 mir_choose_alu(&vmul
, instructions
, liveness
, worklist
, len
, &predicate
, UNIT_VMUL
);
1296 mir_update_worklist(worklist
, len
, instructions
, vmul
);
1297 mir_update_worklist(worklist
, len
, instructions
, sadd
);
1299 bundle
.has_blend_constant
= predicate
.blend_constant
;
1300 bundle
.has_embedded_constants
= predicate
.constant_mask
!= 0;
1302 unsigned padding
= 0;
1304 /* Now that we have finished scheduling, build up the bundle */
1305 midgard_instruction
*stages
[] = { vmul
, sadd
, vadd
, smul
, vlut
, branch
};
1307 for (unsigned i
= 0; i
< ARRAY_SIZE(stages
); ++i
) {
1309 bundle
.control
|= stages
[i
]->unit
;
1310 bytes_emitted
+= bytes_for_instruction(stages
[i
]);
1311 bundle
.instructions
[bundle
.instruction_count
++] = stages
[i
];
1313 /* If we branch, we can't spill to TLS since the store
1314 * instruction will never get executed. We could try to
1315 * break the bundle but this is probably easier for
1319 stages
[i
]->no_spill
|= (1 << REG_CLASS_WORK
);
1323 /* Pad ALU op to nearest word */
1325 if (bytes_emitted
& 15) {
1326 padding
= 16 - (bytes_emitted
& 15);
1327 bytes_emitted
+= padding
;
1330 /* Constants must always be quadwords */
1331 if (bundle
.has_embedded_constants
)
1332 bytes_emitted
+= 16;
1334 /* Size ALU instruction for tag */
1335 bundle
.tag
= (TAG_ALU_4
) + (bytes_emitted
/ 16) - 1;
1337 bool tilebuf_wait
= branch
&& branch
->compact_branch
&&
1338 branch
->branch
.target_type
== TARGET_TILEBUF_WAIT
;
1340 /* MRT capable GPUs use a special writeout procedure */
1341 if ((writeout
|| tilebuf_wait
) && !(ctx
->quirks
& MIDGARD_NO_UPPER_ALU
))
1344 bundle
.padding
= padding
;
1345 bundle
.control
|= bundle
.tag
;
1350 /* Schedule a single block by iterating its instruction to create bundles.
1351 * While we go, tally about the bundle sizes to compute the block size. */
1355 schedule_block(compiler_context
*ctx
, midgard_block
*block
)
1357 /* Copy list to dynamic array */
1359 midgard_instruction
**instructions
= flatten_mir(block
, &len
);
1364 /* Calculate dependencies and initial worklist */
1365 unsigned node_count
= ctx
->temp_count
+ 1;
1366 mir_create_dependency_graph(instructions
, len
, node_count
);
1368 /* Allocate the worklist */
1369 size_t sz
= BITSET_WORDS(len
) * sizeof(BITSET_WORD
);
1370 BITSET_WORD
*worklist
= calloc(sz
, 1);
1371 uint16_t *liveness
= calloc(node_count
, 2);
1372 mir_initialize_worklist(worklist
, instructions
, len
);
1374 struct util_dynarray bundles
;
1375 util_dynarray_init(&bundles
, NULL
);
1377 block
->quadword_count
= 0;
1378 unsigned blend_offset
= 0;
1381 unsigned tag
= mir_choose_bundle(instructions
, liveness
, worklist
, len
);
1382 midgard_bundle bundle
;
1384 if (tag
== TAG_TEXTURE_4
)
1385 bundle
= mir_schedule_texture(instructions
, liveness
, worklist
, len
, ctx
->stage
!= MESA_SHADER_FRAGMENT
);
1386 else if (tag
== TAG_LOAD_STORE_4
)
1387 bundle
= mir_schedule_ldst(instructions
, liveness
, worklist
, len
);
1388 else if (tag
== TAG_ALU_4
)
1389 bundle
= mir_schedule_alu(ctx
, instructions
, liveness
, worklist
, len
);
1393 util_dynarray_append(&bundles
, midgard_bundle
, bundle
);
1395 if (bundle
.has_blend_constant
)
1396 blend_offset
= block
->quadword_count
;
1398 block
->quadword_count
+= midgard_tag_props
[bundle
.tag
].size
;
1401 /* We emitted bundles backwards; copy into the block in reverse-order */
1403 util_dynarray_init(&block
->bundles
, block
);
1404 util_dynarray_foreach_reverse(&bundles
, midgard_bundle
, bundle
) {
1405 util_dynarray_append(&block
->bundles
, midgard_bundle
, *bundle
);
1407 util_dynarray_fini(&bundles
);
1409 /* Blend constant was backwards as well. blend_offset if set is
1410 * strictly positive, as an offset of zero would imply constants before
1411 * any instructions which is invalid in Midgard. TODO: blend constants
1412 * are broken if you spill since then quadword_count becomes invalid
1416 ctx
->blend_constant_offset
= ((ctx
->quadword_count
+ block
->quadword_count
) - blend_offset
- 1) * 0x10;
1418 block
->scheduled
= true;
1419 ctx
->quadword_count
+= block
->quadword_count
;
1421 /* Reorder instructions to match bundled. First remove existing
1422 * instructions and then recreate the list */
1424 mir_foreach_instr_in_block_safe(block
, ins
) {
1425 list_del(&ins
->link
);
1428 mir_foreach_instr_in_block_scheduled_rev(block
, ins
) {
1429 list_add(&ins
->link
, &block
->base
.instructions
);
1432 free(instructions
); /* Allocated by flatten_mir() */
1438 midgard_schedule_program(compiler_context
*ctx
)
1440 midgard_promote_uniforms(ctx
);
1442 /* Must be lowered right before scheduling */
1443 mir_squeeze_index(ctx
);
1444 mir_lower_special_reads(ctx
);
1445 mir_squeeze_index(ctx
);
1447 /* Lowering can introduce some dead moves */
1449 mir_foreach_block(ctx
, _block
) {
1450 midgard_block
*block
= (midgard_block
*) _block
;
1451 midgard_opt_dead_move_eliminate(ctx
, block
);
1452 schedule_block(ctx
, block
);