2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 #include "midgard_ops.h"
26 #include "midgard_quirks.h"
27 #include "util/u_memory.h"
28 #include "util/u_math.h"
30 /* Scheduling for Midgard is complicated, to say the least. ALU instructions
31 * must be grouped into VLIW bundles according to following model:
34 * [VADD] [SMUL] [VLUT]
36 * A given instruction can execute on some subset of the units (or a few can
37 * execute on all). Instructions can be either vector or scalar; only scalar
38 * instructions can execute on SADD/SMUL units. Units on a given line execute
39 * in parallel. Subsequent lines execute separately and can pass results
40 * directly via pipeline registers r24/r25, bypassing the register file.
42 * A bundle can optionally have 128-bits of embedded constants, shared across
43 * all of the instructions within a bundle.
45 * Instructions consuming conditionals (branches and conditional selects)
46 * require their condition to be written into the conditional register (r31)
47 * within the same bundle they are consumed.
49 * Fragment writeout requires its argument to be written in full within the
50 * same bundle as the branch, with no hanging dependencies.
52 * Load/store instructions are also in bundles of simply two instructions, and
53 * texture instructions have no bundling.
55 * -------------------------------------------------------------------------
59 /* We create the dependency graph with per-byte granularity */
64 add_dependency(struct util_dynarray
*table
, unsigned index
, uint16_t mask
, midgard_instruction
**instructions
, unsigned child
)
66 for (unsigned i
= 0; i
< BYTE_COUNT
; ++i
) {
67 if (!(mask
& (1 << i
)))
70 struct util_dynarray
*parents
= &table
[(BYTE_COUNT
* index
) + i
];
72 util_dynarray_foreach(parents
, unsigned, parent
) {
73 BITSET_WORD
*dependents
= instructions
[*parent
]->dependents
;
75 /* Already have the dependency */
76 if (BITSET_TEST(dependents
, child
))
79 BITSET_SET(dependents
, child
);
80 instructions
[child
]->nr_dependencies
++;
86 mark_access(struct util_dynarray
*table
, unsigned index
, uint16_t mask
, unsigned parent
)
88 for (unsigned i
= 0; i
< BYTE_COUNT
; ++i
) {
89 if (!(mask
& (1 << i
)))
92 util_dynarray_append(&table
[(BYTE_COUNT
* index
) + i
], unsigned, parent
);
97 mir_create_dependency_graph(midgard_instruction
**instructions
, unsigned count
, unsigned node_count
)
99 size_t sz
= node_count
* BYTE_COUNT
;
101 struct util_dynarray
*last_read
= calloc(sizeof(struct util_dynarray
), sz
);
102 struct util_dynarray
*last_write
= calloc(sizeof(struct util_dynarray
), sz
);
104 for (unsigned i
= 0; i
< sz
; ++i
) {
105 util_dynarray_init(&last_read
[i
], NULL
);
106 util_dynarray_init(&last_write
[i
], NULL
);
109 /* Initialize dependency graph */
110 for (unsigned i
= 0; i
< count
; ++i
) {
111 instructions
[i
]->dependents
=
112 calloc(BITSET_WORDS(count
), sizeof(BITSET_WORD
));
114 instructions
[i
]->nr_dependencies
= 0;
117 /* Populate dependency graph */
118 for (signed i
= count
- 1; i
>= 0; --i
) {
119 if (instructions
[i
]->compact_branch
)
122 unsigned dest
= instructions
[i
]->dest
;
123 unsigned mask
= mir_bytemask(instructions
[i
]);
125 mir_foreach_src((*instructions
), s
) {
126 unsigned src
= instructions
[i
]->src
[s
];
128 if (src
< node_count
) {
129 unsigned readmask
= mir_bytemask_of_read_components(instructions
[i
], src
);
130 add_dependency(last_write
, src
, readmask
, instructions
, i
);
134 if (dest
< node_count
) {
135 add_dependency(last_read
, dest
, mask
, instructions
, i
);
136 add_dependency(last_write
, dest
, mask
, instructions
, i
);
137 mark_access(last_write
, dest
, mask
, i
);
140 mir_foreach_src((*instructions
), s
) {
141 unsigned src
= instructions
[i
]->src
[s
];
143 if (src
< node_count
) {
144 unsigned readmask
= mir_bytemask_of_read_components(instructions
[i
], src
);
145 mark_access(last_read
, src
, readmask
, i
);
150 /* If there is a branch, all instructions depend on it, as interblock
151 * execution must be purely in-order */
153 if (instructions
[count
- 1]->compact_branch
) {
154 BITSET_WORD
*dependents
= instructions
[count
- 1]->dependents
;
156 for (signed i
= count
- 2; i
>= 0; --i
) {
157 if (BITSET_TEST(dependents
, i
))
160 BITSET_SET(dependents
, i
);
161 instructions
[i
]->nr_dependencies
++;
165 /* Free the intermediate structures */
166 for (unsigned i
= 0; i
< sz
; ++i
) {
167 util_dynarray_fini(&last_read
[i
]);
168 util_dynarray_fini(&last_write
[i
]);
175 /* Does the mask cover more than a scalar? */
178 is_single_component_mask(unsigned mask
)
182 for (int c
= 0; c
< 8; ++c
) {
187 return components
== 1;
190 /* Helpers for scheudling */
193 mir_is_scalar(midgard_instruction
*ains
)
195 /* Do we try to use it as a vector op? */
196 if (!is_single_component_mask(ains
->mask
))
199 /* Otherwise, check mode hazards */
200 bool could_scalar
= true;
201 unsigned sz0
= nir_alu_type_get_type_size(ains
->src_types
[0]);
202 unsigned sz1
= nir_alu_type_get_type_size(ains
->src_types
[1]);
204 /* Only 16/32-bit can run on a scalar unit */
205 could_scalar
&= ains
->alu
.reg_mode
!= midgard_reg_mode_8
;
206 could_scalar
&= ains
->alu
.reg_mode
!= midgard_reg_mode_64
;
208 if (ains
->src
[0] != ~0)
209 could_scalar
&= (sz0
== 16) || (sz0
== 32);
211 if (ains
->src
[1] != ~0)
212 could_scalar
&= (sz1
== 16) || (sz1
== 32);
217 /* How many bytes does this ALU instruction add to the bundle? */
220 bytes_for_instruction(midgard_instruction
*ains
)
222 if (ains
->unit
& UNITS_ANY_VECTOR
)
223 return sizeof(midgard_reg_info
) + sizeof(midgard_vector_alu
);
224 else if (ains
->unit
== ALU_ENAB_BRANCH
)
225 return sizeof(midgard_branch_extended
);
226 else if (ains
->compact_branch
)
227 return sizeof(ains
->br_compact
);
229 return sizeof(midgard_reg_info
) + sizeof(midgard_scalar_alu
);
232 /* We would like to flatten the linked list of midgard_instructions in a bundle
233 * to an array of pointers on the heap for easy indexing */
235 static midgard_instruction
**
236 flatten_mir(midgard_block
*block
, unsigned *len
)
238 *len
= list_length(&block
->base
.instructions
);
243 midgard_instruction
**instructions
=
244 calloc(sizeof(midgard_instruction
*), *len
);
248 mir_foreach_instr_in_block(block
, ins
)
249 instructions
[i
++] = ins
;
254 /* The worklist is the set of instructions that can be scheduled now; that is,
255 * the set of instructions with no remaining dependencies */
258 mir_initialize_worklist(BITSET_WORD
*worklist
, midgard_instruction
**instructions
, unsigned count
)
260 for (unsigned i
= 0; i
< count
; ++i
) {
261 if (instructions
[i
]->nr_dependencies
== 0)
262 BITSET_SET(worklist
, i
);
266 /* Update the worklist after an instruction terminates. Remove its edges from
267 * the graph and if that causes any node to have no dependencies, add it to the
272 BITSET_WORD
*worklist
, unsigned count
,
273 midgard_instruction
**instructions
, midgard_instruction
*done
)
275 /* Sanity check: if no instruction terminated, there is nothing to do.
276 * If the instruction that terminated had dependencies, that makes no
277 * sense and means we messed up the worklist. Finally, as the purpose
278 * of this routine is to update dependents, we abort early if there are
279 * no dependents defined. */
284 assert(done
->nr_dependencies
== 0);
286 if (!done
->dependents
)
289 /* We have an instruction with dependents. Iterate each dependent to
290 * remove one dependency (`done`), adding dependents to the worklist
294 BITSET_FOREACH_SET(i
, done
->dependents
, count
) {
295 assert(instructions
[i
]->nr_dependencies
);
297 if (!(--instructions
[i
]->nr_dependencies
))
298 BITSET_SET(worklist
, i
);
301 free(done
->dependents
);
304 /* While scheduling, we need to choose instructions satisfying certain
305 * criteria. As we schedule backwards, we choose the *last* instruction in the
306 * worklist to simulate in-order scheduling. Chosen instructions must satisfy a
307 * given predicate. */
309 struct midgard_predicate
{
310 /* TAG or ~0 for dont-care */
313 /* True if we want to pop off the chosen instruction */
316 /* For ALU, choose only this unit */
319 /* State for bundle constants. constants is the actual constants
320 * for the bundle. constant_count is the number of bytes (up to
321 * 16) currently in use for constants. When picking in destructive
322 * mode, the constants array will be updated, and the instruction
323 * will be adjusted to index into the constants array */
325 midgard_constants
*constants
;
326 unsigned constant_mask
;
329 /* Exclude this destination (if not ~0) */
332 /* Don't schedule instructions consuming conditionals (since we already
333 * scheduled one). Excludes conditional branches and csel */
336 /* Require a minimal mask and (if nonzero) given destination. Used for
337 * writeout optimizations */
342 /* For load/store: how many pipeline registers are in use? The two
343 * scheduled instructions cannot use more than the 256-bits of pipeline
344 * space available or RA will fail (as it would run out of pipeline
345 * registers and fail to spill without breaking the schedule) */
347 unsigned pipeline_count
;
351 mir_adjust_constant(midgard_instruction
*ins
, unsigned src
,
352 unsigned *bundle_constant_mask
,
353 unsigned *comp_mapping
,
354 uint8_t *bundle_constants
)
356 unsigned type_size
= nir_alu_type_get_type_size(ins
->src_types
[src
]) / 8;
357 unsigned max_comp
= 16 / type_size
;
358 unsigned comp_mask
= mir_from_bytemask(mir_round_bytemask_up(
359 mir_bytemask_of_read_components_index(ins
, src
),
362 unsigned type_mask
= (1 << type_size
) - 1;
364 for (unsigned comp
= 0; comp
< max_comp
; comp
++) {
365 if (!(comp_mask
& (1 << comp
)))
368 uint8_t *constantp
= ins
->constants
.u8
+ (type_size
* comp
);
369 unsigned best_reuse_bytes
= 0;
370 signed best_place
= -1;
373 for (i
= 0; i
< 16; i
+= type_size
) {
374 unsigned reuse_bytes
= 0;
376 for (j
= 0; j
< type_size
; j
++) {
377 if (!(*bundle_constant_mask
& (1 << (i
+ j
))))
379 if (constantp
[j
] != bundle_constants
[i
+ j
])
385 /* Select the place where existing bytes can be
386 * reused so we leave empty slots to others
388 if (j
== type_size
&&
389 (reuse_bytes
> best_reuse_bytes
|| best_place
< 0)) {
390 best_reuse_bytes
= reuse_bytes
;
396 /* This component couldn't fit in the remaining constant slot,
397 * no need check the remaining components, bail out now
402 memcpy(&bundle_constants
[i
], constantp
, type_size
);
403 *bundle_constant_mask
|= type_mask
<< best_place
;
404 comp_mapping
[comp
] = best_place
/ type_size
;
410 /* For an instruction that can fit, adjust it to fit and update the constants
411 * array, in destructive mode. Returns whether the fitting was successful. */
414 mir_adjust_constants(midgard_instruction
*ins
,
415 struct midgard_predicate
*pred
,
418 /* Blend constants dominate */
419 if (ins
->has_blend_constant
) {
420 if (pred
->constant_mask
)
422 else if (destructive
) {
423 pred
->blend_constant
= true;
424 pred
->constant_mask
= 0xffff;
429 /* No constant, nothing to adjust */
430 if (!ins
->has_constants
)
433 unsigned r_constant
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
434 unsigned bundle_constant_mask
= pred
->constant_mask
;
435 unsigned comp_mapping
[2][16] = { };
436 uint8_t bundle_constants
[16];
438 memcpy(bundle_constants
, pred
->constants
, 16);
440 /* Let's try to find a place for each active component of the constant
443 for (unsigned src
= 0; src
< 2; ++src
) {
444 if (ins
->src
[src
] != SSA_FIXED_REGISTER(REGISTER_CONSTANT
))
447 if (!mir_adjust_constant(ins
, src
, &bundle_constant_mask
,
448 comp_mapping
[src
], bundle_constants
))
452 /* If non-destructive, we're done */
456 /* Otherwise update the constant_mask and constant values */
457 pred
->constant_mask
= bundle_constant_mask
;
458 memcpy(pred
->constants
, bundle_constants
, 16);
460 /* Use comp_mapping as a swizzle */
461 mir_foreach_src(ins
, s
) {
462 if (ins
->src
[s
] == r_constant
)
463 mir_compose_swizzle(ins
->swizzle
[s
], comp_mapping
[s
], ins
->swizzle
[s
]);
469 /* Conservative estimate of the pipeline registers required for load/store */
472 mir_pipeline_count(midgard_instruction
*ins
)
474 unsigned bytecount
= 0;
476 mir_foreach_src(ins
, i
) {
477 /* Skip empty source */
478 if (ins
->src
[i
] == ~0) continue;
480 unsigned bytemask
= mir_bytemask_of_read_components_index(ins
, i
);
482 unsigned max
= util_logbase2(bytemask
) + 1;
486 return DIV_ROUND_UP(bytecount
, 16);
489 static midgard_instruction
*
490 mir_choose_instruction(
491 midgard_instruction
**instructions
,
492 BITSET_WORD
*worklist
, unsigned count
,
493 struct midgard_predicate
*predicate
)
495 /* Parse the predicate */
496 unsigned tag
= predicate
->tag
;
497 bool alu
= tag
== TAG_ALU_4
;
498 bool ldst
= tag
== TAG_LOAD_STORE_4
;
499 unsigned unit
= predicate
->unit
;
500 bool branch
= alu
&& (unit
== ALU_ENAB_BR_COMPACT
);
501 bool scalar
= (unit
!= ~0) && (unit
& UNITS_SCALAR
);
502 bool no_cond
= predicate
->no_cond
;
504 unsigned mask
= predicate
->mask
;
505 unsigned dest
= predicate
->dest
;
506 bool needs_dest
= mask
& 0xF;
508 /* Iterate to find the best instruction satisfying the predicate */
511 signed best_index
= -1;
512 bool best_conditional
= false;
514 /* Enforce a simple metric limiting distance to keep down register
515 * pressure. TOOD: replace with liveness tracking for much better
518 unsigned max_active
= 0;
519 unsigned max_distance
= 6;
521 BITSET_FOREACH_SET(i
, worklist
, count
) {
522 max_active
= MAX2(max_active
, i
);
525 BITSET_FOREACH_SET(i
, worklist
, count
) {
526 if ((max_active
- i
) >= max_distance
)
529 if (tag
!= ~0 && instructions
[i
]->type
!= tag
)
532 if (predicate
->exclude
!= ~0 && instructions
[i
]->dest
== predicate
->exclude
)
535 if (alu
&& !branch
&& !(alu_opcode_props
[instructions
[i
]->alu
.op
].props
& unit
))
538 if (branch
&& !instructions
[i
]->compact_branch
)
541 if (alu
&& scalar
&& !mir_is_scalar(instructions
[i
]))
544 if (alu
&& !mir_adjust_constants(instructions
[i
], predicate
, false))
547 if (needs_dest
&& instructions
[i
]->dest
!= dest
)
550 if (mask
&& ((~instructions
[i
]->mask
) & mask
))
553 if (ldst
&& mir_pipeline_count(instructions
[i
]) + predicate
->pipeline_count
> 2)
556 bool conditional
= alu
&& !branch
&& OP_IS_CSEL(instructions
[i
]->alu
.op
);
557 conditional
|= (branch
&& instructions
[i
]->branch
.conditional
);
559 if (conditional
&& no_cond
)
562 /* Simulate in-order scheduling */
563 if ((signed) i
< best_index
)
567 best_conditional
= conditional
;
571 /* Did we find anything? */
576 /* If we found something, remove it from the worklist */
577 assert(best_index
< count
);
579 if (predicate
->destructive
) {
580 BITSET_CLEAR(worklist
, best_index
);
583 mir_adjust_constants(instructions
[best_index
], predicate
, true);
586 predicate
->pipeline_count
+= mir_pipeline_count(instructions
[best_index
]);
588 /* Once we schedule a conditional, we can't again */
589 predicate
->no_cond
|= best_conditional
;
592 return instructions
[best_index
];
595 /* Still, we don't choose instructions in a vacuum. We need a way to choose the
596 * best bundle type (ALU, load/store, texture). Nondestructive. */
600 midgard_instruction
**instructions
,
601 BITSET_WORD
*worklist
, unsigned count
)
603 /* At the moment, our algorithm is very simple - use the bundle of the
604 * best instruction, regardless of what else could be scheduled
605 * alongside it. This is not optimal but it works okay for in-order */
607 struct midgard_predicate predicate
= {
609 .destructive
= false,
613 midgard_instruction
*chosen
= mir_choose_instruction(instructions
, worklist
, count
, &predicate
);
621 /* We want to choose an ALU instruction filling a given unit */
623 mir_choose_alu(midgard_instruction
**slot
,
624 midgard_instruction
**instructions
,
625 BITSET_WORD
*worklist
, unsigned len
,
626 struct midgard_predicate
*predicate
,
629 /* Did we already schedule to this slot? */
633 /* Try to schedule something, if not */
634 predicate
->unit
= unit
;
635 *slot
= mir_choose_instruction(instructions
, worklist
, len
, predicate
);
637 /* Store unit upon scheduling */
638 if (*slot
&& !((*slot
)->compact_branch
))
639 (*slot
)->unit
= unit
;
642 /* When we are scheduling a branch/csel, we need the consumed condition in the
643 * same block as a pipeline register. There are two options to enable this:
645 * - Move the conditional into the bundle. Preferred, but only works if the
646 * conditional is used only once and is from this block.
647 * - Copy the conditional.
649 * We search for the conditional. If it's in this block, single-use, and
650 * without embedded constants, we schedule it immediately. Otherwise, we
651 * schedule a move for it.
653 * mir_comparison_mobile is a helper to find the moveable condition.
657 mir_comparison_mobile(
658 compiler_context
*ctx
,
659 midgard_instruction
**instructions
,
660 struct midgard_predicate
*predicate
,
664 if (!mir_single_use(ctx
, cond
))
669 for (unsigned i
= 0; i
< count
; ++i
) {
670 if (instructions
[i
]->dest
!= cond
)
673 /* Must fit in an ALU bundle */
674 if (instructions
[i
]->type
!= TAG_ALU_4
)
677 /* If it would itself require a condition, that's recursive */
678 if (OP_IS_CSEL(instructions
[i
]->alu
.op
))
681 /* We'll need to rewrite to .w but that doesn't work for vector
682 * ops that don't replicate (ball/bany), so bail there */
684 if (GET_CHANNEL_COUNT(alu_opcode_props
[instructions
[i
]->alu
.op
].props
))
687 /* Ensure it will fit with constants */
689 if (!mir_adjust_constants(instructions
[i
], predicate
, false))
692 /* Ensure it is written only once */
700 /* Inject constants now that we are sure we want to */
702 mir_adjust_constants(instructions
[ret
], predicate
, true);
707 /* Using the information about the moveable conditional itself, we either pop
708 * that condition off the worklist for use now, or create a move to
709 * artificially schedule instead as a fallback */
711 static midgard_instruction
*
712 mir_schedule_comparison(
713 compiler_context
*ctx
,
714 midgard_instruction
**instructions
,
715 struct midgard_predicate
*predicate
,
716 BITSET_WORD
*worklist
, unsigned count
,
717 unsigned cond
, bool vector
, unsigned *swizzle
,
718 midgard_instruction
*user
)
720 /* TODO: swizzle when scheduling */
722 (!vector
&& (swizzle
[0] == 0)) ?
723 mir_comparison_mobile(ctx
, instructions
, predicate
, count
, cond
) : ~0;
725 /* If we can, schedule the condition immediately */
726 if ((comp_i
!= ~0) && BITSET_TEST(worklist
, comp_i
)) {
727 assert(comp_i
< count
);
728 BITSET_CLEAR(worklist
, comp_i
);
729 return instructions
[comp_i
];
732 /* Otherwise, we insert a move */
734 midgard_instruction mov
= v_mov(cond
, cond
);
735 mov
.mask
= vector
? 0xF : 0x1;
736 memcpy(mov
.swizzle
[1], swizzle
, sizeof(mov
.swizzle
[1]));
738 return mir_insert_instruction_before(ctx
, user
, mov
);
741 /* Most generally, we need instructions writing to r31 in the appropriate
744 static midgard_instruction
*
745 mir_schedule_condition(compiler_context
*ctx
,
746 struct midgard_predicate
*predicate
,
747 BITSET_WORD
*worklist
, unsigned count
,
748 midgard_instruction
**instructions
,
749 midgard_instruction
*last
)
751 /* For a branch, the condition is the only argument; for csel, third */
752 bool branch
= last
->compact_branch
;
753 unsigned condition_index
= branch
? 0 : 2;
755 /* csel_v is vector; otherwise, conditions are scalar */
756 bool vector
= !branch
&& OP_IS_CSEL_V(last
->alu
.op
);
758 /* Grab the conditional instruction */
760 midgard_instruction
*cond
= mir_schedule_comparison(
761 ctx
, instructions
, predicate
, worklist
, count
, last
->src
[condition_index
],
762 vector
, last
->swizzle
[2], last
);
764 /* We have exclusive reign over this (possibly move) conditional
765 * instruction. We can rewrite into a pipeline conditional register */
767 predicate
->exclude
= cond
->dest
;
768 cond
->dest
= SSA_FIXED_REGISTER(31);
771 cond
->mask
= (1 << COMPONENT_W
);
773 mir_foreach_src(cond
, s
) {
774 if (cond
->src
[s
] == ~0)
777 for (unsigned q
= 0; q
< 4; ++q
)
778 cond
->swizzle
[s
][q
+ COMPONENT_W
] = cond
->swizzle
[s
][q
];
782 /* Schedule the unit: csel is always in the latter pipeline, so a csel
783 * condition must be in the former pipeline stage (vmul/sadd),
784 * depending on scalar/vector of the instruction itself. A branch must
785 * be written from the latter pipeline stage and a branch condition is
786 * always scalar, so it is always in smul (exception: ball/bany, which
790 cond
->unit
= UNIT_SMUL
;
792 cond
->unit
= vector
? UNIT_VMUL
: UNIT_SADD
;
797 /* Schedules a single bundle of the given type */
799 static midgard_bundle
800 mir_schedule_texture(
801 midgard_instruction
**instructions
,
802 BITSET_WORD
*worklist
, unsigned len
)
804 struct midgard_predicate predicate
= {
805 .tag
= TAG_TEXTURE_4
,
810 midgard_instruction
*ins
=
811 mir_choose_instruction(instructions
, worklist
, len
, &predicate
);
813 mir_update_worklist(worklist
, len
, instructions
, ins
);
815 struct midgard_bundle out
= {
816 .tag
= ins
->texture
.op
== TEXTURE_OP_BARRIER
?
817 TAG_TEXTURE_4_BARRIER
: TAG_TEXTURE_4
,
818 .instruction_count
= 1,
819 .instructions
= { ins
}
825 static midgard_bundle
827 midgard_instruction
**instructions
,
828 BITSET_WORD
*worklist
, unsigned len
)
830 struct midgard_predicate predicate
= {
831 .tag
= TAG_LOAD_STORE_4
,
836 /* Try to pick two load/store ops. Second not gauranteed to exist */
838 midgard_instruction
*ins
=
839 mir_choose_instruction(instructions
, worklist
, len
, &predicate
);
841 midgard_instruction
*pair
=
842 mir_choose_instruction(instructions
, worklist
, len
, &predicate
);
844 struct midgard_bundle out
= {
845 .tag
= TAG_LOAD_STORE_4
,
846 .instruction_count
= pair
? 2 : 1,
847 .instructions
= { ins
, pair
}
850 /* We have to update the worklist atomically, since the two
851 * instructions run concurrently (TODO: verify it's not pipelined) */
853 mir_update_worklist(worklist
, len
, instructions
, ins
);
854 mir_update_worklist(worklist
, len
, instructions
, pair
);
859 static midgard_bundle
861 compiler_context
*ctx
,
862 midgard_instruction
**instructions
,
863 BITSET_WORD
*worklist
, unsigned len
)
865 struct midgard_bundle bundle
= {};
867 unsigned bytes_emitted
= sizeof(bundle
.control
);
869 struct midgard_predicate predicate
= {
873 .constants
= &bundle
.constants
876 midgard_instruction
*vmul
= NULL
;
877 midgard_instruction
*vadd
= NULL
;
878 midgard_instruction
*vlut
= NULL
;
879 midgard_instruction
*smul
= NULL
;
880 midgard_instruction
*sadd
= NULL
;
881 midgard_instruction
*branch
= NULL
;
883 mir_choose_alu(&branch
, instructions
, worklist
, len
, &predicate
, ALU_ENAB_BR_COMPACT
);
884 mir_update_worklist(worklist
, len
, instructions
, branch
);
885 bool writeout
= branch
&& branch
->writeout
;
886 bool zs_writeout
= writeout
&& (branch
->writeout_depth
| branch
->writeout_stencil
);
888 if (branch
&& branch
->branch
.conditional
) {
889 midgard_instruction
*cond
= mir_schedule_condition(ctx
, &predicate
, worklist
, len
, instructions
, branch
);
891 if (cond
->unit
== UNIT_VADD
)
893 else if (cond
->unit
== UNIT_SMUL
)
896 unreachable("Bad condition");
899 /* If we have a render target reference, schedule a move for it. Since
900 * this will be in sadd, we boost this to prevent scheduling csel into
903 if (writeout
&& (branch
->constants
.u32
[0] || ctx
->is_blend
)) {
904 sadd
= ralloc(ctx
, midgard_instruction
);
905 *sadd
= v_mov(~0, make_compiler_temp(ctx
));
906 sadd
->unit
= UNIT_SADD
;
908 sadd
->has_inline_constant
= true;
909 sadd
->inline_constant
= branch
->constants
.u32
[0];
910 branch
->src
[1] = sadd
->dest
;
911 branch
->src_types
[1] = sadd
->dest_type
;
913 /* Mask off any conditionals. Could be optimized to just scalar
914 * conditionals TODO */
915 predicate
.no_cond
= true;
918 mir_choose_alu(&smul
, instructions
, worklist
, len
, &predicate
, UNIT_SMUL
);
921 mir_choose_alu(&vlut
, instructions
, worklist
, len
, &predicate
, UNIT_VLUT
);
924 bundle
.last_writeout
= branch
->last_writeout
;
927 if (writeout
&& !zs_writeout
) {
928 vadd
= ralloc(ctx
, midgard_instruction
);
929 *vadd
= v_mov(~0, make_compiler_temp(ctx
));
931 if (!ctx
->is_blend
) {
932 vadd
->alu
.op
= midgard_alu_op_iadd
;
933 vadd
->src
[0] = SSA_FIXED_REGISTER(31);
934 vadd
->src_types
[0] = nir_type_uint32
;
936 for (unsigned c
= 0; c
< 16; ++c
)
937 vadd
->swizzle
[0][c
] = COMPONENT_X
;
939 vadd
->has_inline_constant
= true;
940 vadd
->inline_constant
= 0;
942 vadd
->src
[1] = SSA_FIXED_REGISTER(1);
943 vadd
->src_types
[0] = nir_type_uint32
;
945 for (unsigned c
= 0; c
< 16; ++c
)
946 vadd
->swizzle
[1][c
] = COMPONENT_W
;
949 vadd
->unit
= UNIT_VADD
;
951 branch
->src
[2] = vadd
->dest
;
952 branch
->src_types
[2] = vadd
->dest_type
;
955 mir_choose_alu(&vadd
, instructions
, worklist
, len
, &predicate
, UNIT_VADD
);
957 mir_update_worklist(worklist
, len
, instructions
, vlut
);
958 mir_update_worklist(worklist
, len
, instructions
, vadd
);
959 mir_update_worklist(worklist
, len
, instructions
, smul
);
961 bool vadd_csel
= vadd
&& OP_IS_CSEL(vadd
->alu
.op
);
962 bool smul_csel
= smul
&& OP_IS_CSEL(smul
->alu
.op
);
964 if (vadd_csel
|| smul_csel
) {
965 midgard_instruction
*ins
= vadd_csel
? vadd
: smul
;
966 midgard_instruction
*cond
= mir_schedule_condition(ctx
, &predicate
, worklist
, len
, instructions
, ins
);
968 if (cond
->unit
== UNIT_VMUL
)
970 else if (cond
->unit
== UNIT_SADD
)
973 unreachable("Bad condition");
976 /* Stage 2, let's schedule sadd before vmul for writeout */
977 mir_choose_alu(&sadd
, instructions
, worklist
, len
, &predicate
, UNIT_SADD
);
979 /* Check if writeout reads its own register */
982 midgard_instruction
*stages
[] = { sadd
, vadd
, smul
};
983 unsigned src
= (branch
->src
[0] == ~0) ? SSA_FIXED_REGISTER(zs_writeout
? 1 : 0) : branch
->src
[0];
984 unsigned writeout_mask
= 0x0;
985 bool bad_writeout
= false;
987 for (unsigned i
= 0; i
< ARRAY_SIZE(stages
); ++i
) {
991 if (stages
[i
]->dest
!= src
)
994 writeout_mask
|= stages
[i
]->mask
;
995 bad_writeout
|= mir_has_arg(stages
[i
], branch
->src
[0]);
998 /* It's possible we'll be able to schedule something into vmul
999 * to fill r0/r1. Let's peak into the future, trying to schedule
1000 * vmul specially that way. */
1002 unsigned full_mask
= zs_writeout
?
1003 (1 << (branch
->writeout_depth
+ branch
->writeout_stencil
)) - 1 :
1006 if (!bad_writeout
&& writeout_mask
!= full_mask
) {
1007 predicate
.unit
= UNIT_VMUL
;
1008 predicate
.dest
= src
;
1009 predicate
.mask
= writeout_mask
^ full_mask
;
1011 struct midgard_instruction
*peaked
=
1012 mir_choose_instruction(instructions
, worklist
, len
, &predicate
);
1016 vmul
->unit
= UNIT_VMUL
;
1017 writeout_mask
|= predicate
.mask
;
1018 assert(writeout_mask
== full_mask
);
1022 predicate
.dest
= predicate
.mask
= 0;
1025 /* Finally, add a move if necessary */
1026 if (bad_writeout
|| writeout_mask
!= full_mask
) {
1027 unsigned temp
= (branch
->src
[0] == ~0) ? SSA_FIXED_REGISTER(zs_writeout
? 1 : 0) : make_compiler_temp(ctx
);
1029 vmul
= ralloc(ctx
, midgard_instruction
);
1030 *vmul
= v_mov(src
, temp
);
1031 vmul
->unit
= UNIT_VMUL
;
1032 vmul
->mask
= full_mask
^ writeout_mask
;
1034 /* Rewrite to use our temp */
1036 for (unsigned i
= 0; i
< ARRAY_SIZE(stages
); ++i
) {
1038 mir_rewrite_index_dst_single(stages
[i
], src
, temp
);
1041 mir_rewrite_index_src_single(branch
, src
, temp
);
1045 mir_choose_alu(&vmul
, instructions
, worklist
, len
, &predicate
, UNIT_VMUL
);
1047 mir_update_worklist(worklist
, len
, instructions
, vmul
);
1048 mir_update_worklist(worklist
, len
, instructions
, sadd
);
1050 bundle
.has_blend_constant
= predicate
.blend_constant
;
1051 bundle
.has_embedded_constants
= predicate
.constant_mask
!= 0;
1053 unsigned padding
= 0;
1055 /* Now that we have finished scheduling, build up the bundle */
1056 midgard_instruction
*stages
[] = { vmul
, sadd
, vadd
, smul
, vlut
, branch
};
1058 for (unsigned i
= 0; i
< ARRAY_SIZE(stages
); ++i
) {
1060 bundle
.control
|= stages
[i
]->unit
;
1061 bytes_emitted
+= bytes_for_instruction(stages
[i
]);
1062 bundle
.instructions
[bundle
.instruction_count
++] = stages
[i
];
1064 /* If we branch, we can't spill to TLS since the store
1065 * instruction will never get executed. We could try to
1066 * break the bundle but this is probably easier for
1070 stages
[i
]->no_spill
|= (1 << REG_CLASS_WORK
);
1074 /* Pad ALU op to nearest word */
1076 if (bytes_emitted
& 15) {
1077 padding
= 16 - (bytes_emitted
& 15);
1078 bytes_emitted
+= padding
;
1081 /* Constants must always be quadwords */
1082 if (bundle
.has_embedded_constants
)
1083 bytes_emitted
+= 16;
1085 /* Size ALU instruction for tag */
1086 bundle
.tag
= (TAG_ALU_4
) + (bytes_emitted
/ 16) - 1;
1088 /* MRT capable GPUs use a special writeout procedure */
1089 if (writeout
&& !(ctx
->quirks
& MIDGARD_NO_UPPER_ALU
))
1092 bundle
.padding
= padding
;
1093 bundle
.control
|= bundle
.tag
;
1098 /* Schedule a single block by iterating its instruction to create bundles.
1099 * While we go, tally about the bundle sizes to compute the block size. */
1103 schedule_block(compiler_context
*ctx
, midgard_block
*block
)
1105 /* Copy list to dynamic array */
1107 midgard_instruction
**instructions
= flatten_mir(block
, &len
);
1112 /* Calculate dependencies and initial worklist */
1113 unsigned node_count
= ctx
->temp_count
+ 1;
1114 mir_create_dependency_graph(instructions
, len
, node_count
);
1116 /* Allocate the worklist */
1117 size_t sz
= BITSET_WORDS(len
) * sizeof(BITSET_WORD
);
1118 BITSET_WORD
*worklist
= calloc(sz
, 1);
1119 mir_initialize_worklist(worklist
, instructions
, len
);
1121 struct util_dynarray bundles
;
1122 util_dynarray_init(&bundles
, NULL
);
1124 block
->quadword_count
= 0;
1125 unsigned blend_offset
= 0;
1128 unsigned tag
= mir_choose_bundle(instructions
, worklist
, len
);
1129 midgard_bundle bundle
;
1131 if (tag
== TAG_TEXTURE_4
)
1132 bundle
= mir_schedule_texture(instructions
, worklist
, len
);
1133 else if (tag
== TAG_LOAD_STORE_4
)
1134 bundle
= mir_schedule_ldst(instructions
, worklist
, len
);
1135 else if (tag
== TAG_ALU_4
)
1136 bundle
= mir_schedule_alu(ctx
, instructions
, worklist
, len
);
1140 util_dynarray_append(&bundles
, midgard_bundle
, bundle
);
1142 if (bundle
.has_blend_constant
)
1143 blend_offset
= block
->quadword_count
;
1145 block
->quadword_count
+= midgard_tag_props
[bundle
.tag
].size
;
1148 /* We emitted bundles backwards; copy into the block in reverse-order */
1150 util_dynarray_init(&block
->bundles
, block
);
1151 util_dynarray_foreach_reverse(&bundles
, midgard_bundle
, bundle
) {
1152 util_dynarray_append(&block
->bundles
, midgard_bundle
, *bundle
);
1154 util_dynarray_fini(&bundles
);
1156 /* Blend constant was backwards as well. blend_offset if set is
1157 * strictly positive, as an offset of zero would imply constants before
1158 * any instructions which is invalid in Midgard. TODO: blend constants
1159 * are broken if you spill since then quadword_count becomes invalid
1163 ctx
->blend_constant_offset
= ((ctx
->quadword_count
+ block
->quadword_count
) - blend_offset
- 1) * 0x10;
1165 block
->scheduled
= true;
1166 ctx
->quadword_count
+= block
->quadword_count
;
1168 /* Reorder instructions to match bundled. First remove existing
1169 * instructions and then recreate the list */
1171 mir_foreach_instr_in_block_safe(block
, ins
) {
1172 list_del(&ins
->link
);
1175 mir_foreach_instr_in_block_scheduled_rev(block
, ins
) {
1176 list_add(&ins
->link
, &block
->base
.instructions
);
1179 free(instructions
); /* Allocated by flatten_mir() */
1184 midgard_schedule_program(compiler_context
*ctx
)
1186 midgard_promote_uniforms(ctx
);
1188 /* Must be lowered right before scheduling */
1189 mir_squeeze_index(ctx
);
1190 mir_lower_special_reads(ctx
);
1191 mir_squeeze_index(ctx
);
1193 /* Lowering can introduce some dead moves */
1195 mir_foreach_block(ctx
, _block
) {
1196 midgard_block
*block
= (midgard_block
*) _block
;
1197 midgard_opt_dead_move_eliminate(ctx
, block
);
1198 schedule_block(ctx
, block
);