2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 #include "midgard_ops.h"
26 #include "midgard_quirks.h"
27 #include "util/u_memory.h"
29 /* Scheduling for Midgard is complicated, to say the least. ALU instructions
30 * must be grouped into VLIW bundles according to following model:
33 * [VADD] [SMUL] [VLUT]
35 * A given instruction can execute on some subset of the units (or a few can
36 * execute on all). Instructions can be either vector or scalar; only scalar
37 * instructions can execute on SADD/SMUL units. Units on a given line execute
38 * in parallel. Subsequent lines execute separately and can pass results
39 * directly via pipeline registers r24/r25, bypassing the register file.
41 * A bundle can optionally have 128-bits of embedded constants, shared across
42 * all of the instructions within a bundle.
44 * Instructions consuming conditionals (branches and conditional selects)
45 * require their condition to be written into the conditional register (r31)
46 * within the same bundle they are consumed.
48 * Fragment writeout requires its argument to be written in full within the
49 * same bundle as the branch, with no hanging dependencies.
51 * Load/store instructions are also in bundles of simply two instructions, and
52 * texture instructions have no bundling.
54 * -------------------------------------------------------------------------
58 /* We create the dependency graph with per-byte granularity */
63 add_dependency(struct util_dynarray
*table
, unsigned index
, uint16_t mask
, midgard_instruction
**instructions
, unsigned child
)
65 for (unsigned i
= 0; i
< BYTE_COUNT
; ++i
) {
66 if (!(mask
& (1 << i
)))
69 struct util_dynarray
*parents
= &table
[(BYTE_COUNT
* index
) + i
];
71 util_dynarray_foreach(parents
, unsigned, parent
) {
72 BITSET_WORD
*dependents
= instructions
[*parent
]->dependents
;
74 /* Already have the dependency */
75 if (BITSET_TEST(dependents
, child
))
78 BITSET_SET(dependents
, child
);
79 instructions
[child
]->nr_dependencies
++;
85 mark_access(struct util_dynarray
*table
, unsigned index
, uint16_t mask
, unsigned parent
)
87 for (unsigned i
= 0; i
< BYTE_COUNT
; ++i
) {
88 if (!(mask
& (1 << i
)))
91 util_dynarray_append(&table
[(BYTE_COUNT
* index
) + i
], unsigned, parent
);
96 mir_create_dependency_graph(midgard_instruction
**instructions
, unsigned count
, unsigned node_count
)
98 size_t sz
= node_count
* BYTE_COUNT
;
100 struct util_dynarray
*last_read
= calloc(sizeof(struct util_dynarray
), sz
);
101 struct util_dynarray
*last_write
= calloc(sizeof(struct util_dynarray
), sz
);
103 for (unsigned i
= 0; i
< sz
; ++i
) {
104 util_dynarray_init(&last_read
[i
], NULL
);
105 util_dynarray_init(&last_write
[i
], NULL
);
108 /* Initialize dependency graph */
109 for (unsigned i
= 0; i
< count
; ++i
) {
110 instructions
[i
]->dependents
=
111 calloc(BITSET_WORDS(count
), sizeof(BITSET_WORD
));
113 instructions
[i
]->nr_dependencies
= 0;
116 /* Populate dependency graph */
117 for (signed i
= count
- 1; i
>= 0; --i
) {
118 if (instructions
[i
]->compact_branch
)
121 unsigned dest
= instructions
[i
]->dest
;
122 unsigned mask
= mir_bytemask(instructions
[i
]);
124 mir_foreach_src((*instructions
), s
) {
125 unsigned src
= instructions
[i
]->src
[s
];
127 if (src
< node_count
) {
128 unsigned readmask
= mir_bytemask_of_read_components(instructions
[i
], src
);
129 add_dependency(last_write
, src
, readmask
, instructions
, i
);
133 if (dest
< node_count
) {
134 add_dependency(last_read
, dest
, mask
, instructions
, i
);
135 add_dependency(last_write
, dest
, mask
, instructions
, i
);
136 mark_access(last_write
, dest
, mask
, i
);
139 mir_foreach_src((*instructions
), s
) {
140 unsigned src
= instructions
[i
]->src
[s
];
142 if (src
< node_count
) {
143 unsigned readmask
= mir_bytemask_of_read_components(instructions
[i
], src
);
144 mark_access(last_read
, src
, readmask
, i
);
149 /* If there is a branch, all instructions depend on it, as interblock
150 * execution must be purely in-order */
152 if (instructions
[count
- 1]->compact_branch
) {
153 BITSET_WORD
*dependents
= instructions
[count
- 1]->dependents
;
155 for (signed i
= count
- 2; i
>= 0; --i
) {
156 if (BITSET_TEST(dependents
, i
))
159 BITSET_SET(dependents
, i
);
160 instructions
[i
]->nr_dependencies
++;
164 /* Free the intermediate structures */
165 for (unsigned i
= 0; i
< sz
; ++i
) {
166 util_dynarray_fini(&last_read
[i
]);
167 util_dynarray_fini(&last_write
[i
]);
174 /* Does the mask cover more than a scalar? */
177 is_single_component_mask(unsigned mask
)
181 for (int c
= 0; c
< 8; ++c
) {
186 return components
== 1;
189 /* Helpers for scheudling */
192 mir_is_scalar(midgard_instruction
*ains
)
194 /* Do we try to use it as a vector op? */
195 if (!is_single_component_mask(ains
->mask
))
198 /* Otherwise, check mode hazards */
199 bool could_scalar
= true;
201 /* Only 16/32-bit can run on a scalar unit */
202 could_scalar
&= ains
->alu
.reg_mode
!= midgard_reg_mode_8
;
203 could_scalar
&= ains
->alu
.reg_mode
!= midgard_reg_mode_64
;
204 could_scalar
&= ains
->alu
.dest_override
== midgard_dest_override_none
;
206 if (ains
->alu
.reg_mode
== midgard_reg_mode_16
) {
207 /* If we're running in 16-bit mode, we
208 * can't have any 8-bit sources on the
209 * scalar unit (since the scalar unit
210 * doesn't understand 8-bit) */
212 midgard_vector_alu_src s1
=
213 vector_alu_from_unsigned(ains
->alu
.src1
);
215 could_scalar
&= !s1
.half
;
217 midgard_vector_alu_src s2
=
218 vector_alu_from_unsigned(ains
->alu
.src2
);
220 could_scalar
&= !s2
.half
;
226 /* How many bytes does this ALU instruction add to the bundle? */
229 bytes_for_instruction(midgard_instruction
*ains
)
231 if (ains
->unit
& UNITS_ANY_VECTOR
)
232 return sizeof(midgard_reg_info
) + sizeof(midgard_vector_alu
);
233 else if (ains
->unit
== ALU_ENAB_BRANCH
)
234 return sizeof(midgard_branch_extended
);
235 else if (ains
->compact_branch
)
236 return sizeof(ains
->br_compact
);
238 return sizeof(midgard_reg_info
) + sizeof(midgard_scalar_alu
);
241 /* We would like to flatten the linked list of midgard_instructions in a bundle
242 * to an array of pointers on the heap for easy indexing */
244 static midgard_instruction
**
245 flatten_mir(midgard_block
*block
, unsigned *len
)
247 *len
= list_length(&block
->instructions
);
252 midgard_instruction
**instructions
=
253 calloc(sizeof(midgard_instruction
*), *len
);
257 mir_foreach_instr_in_block(block
, ins
)
258 instructions
[i
++] = ins
;
263 /* The worklist is the set of instructions that can be scheduled now; that is,
264 * the set of instructions with no remaining dependencies */
267 mir_initialize_worklist(BITSET_WORD
*worklist
, midgard_instruction
**instructions
, unsigned count
)
269 for (unsigned i
= 0; i
< count
; ++i
) {
270 if (instructions
[i
]->nr_dependencies
== 0)
271 BITSET_SET(worklist
, i
);
275 /* Update the worklist after an instruction terminates. Remove its edges from
276 * the graph and if that causes any node to have no dependencies, add it to the
281 BITSET_WORD
*worklist
, unsigned count
,
282 midgard_instruction
**instructions
, midgard_instruction
*done
)
284 /* Sanity check: if no instruction terminated, there is nothing to do.
285 * If the instruction that terminated had dependencies, that makes no
286 * sense and means we messed up the worklist. Finally, as the purpose
287 * of this routine is to update dependents, we abort early if there are
288 * no dependents defined. */
293 assert(done
->nr_dependencies
== 0);
295 if (!done
->dependents
)
298 /* We have an instruction with dependents. Iterate each dependent to
299 * remove one dependency (`done`), adding dependents to the worklist
304 BITSET_FOREACH_SET(i
, tmp
, done
->dependents
, count
) {
305 assert(instructions
[i
]->nr_dependencies
);
307 if (!(--instructions
[i
]->nr_dependencies
))
308 BITSET_SET(worklist
, i
);
311 free(done
->dependents
);
314 /* While scheduling, we need to choose instructions satisfying certain
315 * criteria. As we schedule backwards, we choose the *last* instruction in the
316 * worklist to simulate in-order scheduling. Chosen instructions must satisfy a
317 * given predicate. */
319 struct midgard_predicate
{
320 /* TAG or ~0 for dont-care */
323 /* True if we want to pop off the chosen instruction */
326 /* For ALU, choose only this unit */
329 /* State for bundle constants. constants is the actual constants
330 * for the bundle. constant_count is the number of bytes (up to
331 * 16) currently in use for constants. When picking in destructive
332 * mode, the constants array will be updated, and the instruction
333 * will be adjusted to index into the constants array */
335 midgard_constants
*constants
;
336 unsigned constant_mask
;
339 /* Exclude this destination (if not ~0) */
342 /* Don't schedule instructions consuming conditionals (since we already
343 * scheduled one). Excludes conditional branches and csel */
346 /* Require a minimal mask and (if nonzero) given destination. Used for
347 * writeout optimizations */
353 /* For an instruction that can fit, adjust it to fit and update the constants
354 * array, in destructive mode. Returns whether the fitting was successful. */
357 mir_adjust_constants(midgard_instruction
*ins
,
358 struct midgard_predicate
*pred
,
361 /* Blend constants dominate */
362 if (ins
->has_blend_constant
) {
363 if (pred
->constant_mask
)
365 else if (destructive
) {
366 pred
->blend_constant
= true;
367 pred
->constant_mask
= 0xffff;
372 /* No constant, nothing to adjust */
373 if (!ins
->has_constants
)
376 unsigned r_constant
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
377 midgard_reg_mode reg_mode
= ins
->alu
.reg_mode
;
379 midgard_vector_alu_src const_src
= { };
381 if (ins
->src
[0] == r_constant
)
382 const_src
= vector_alu_from_unsigned(ins
->alu
.src1
);
383 else if (ins
->src
[1] == r_constant
)
384 const_src
= vector_alu_from_unsigned(ins
->alu
.src2
);
386 unsigned type_size
= mir_bytes_for_mode(reg_mode
);
388 /* If the ALU is converting up we need to divide type_size by 2 */
392 unsigned max_comp
= 16 / type_size
;
393 unsigned comp_mask
= mir_from_bytemask(mir_bytemask_of_read_components(ins
, r_constant
),
395 unsigned type_mask
= (1 << type_size
) - 1;
396 unsigned bundle_constant_mask
= pred
->constant_mask
;
397 unsigned comp_mapping
[16] = { };
398 uint8_t bundle_constants
[16];
400 memcpy(bundle_constants
, pred
->constants
, 16);
402 /* Let's try to find a place for each active component of the constant
405 for (unsigned comp
= 0; comp
< max_comp
; comp
++) {
406 if (!(comp_mask
& (1 << comp
)))
409 uint8_t *constantp
= ins
->constants
.u8
+ (type_size
* comp
);
410 unsigned best_reuse_bytes
= 0;
411 signed best_place
= -1;
414 for (i
= 0; i
< 16; i
+= type_size
) {
415 unsigned reuse_bytes
= 0;
417 for (j
= 0; j
< type_size
; j
++) {
418 if (!(bundle_constant_mask
& (1 << (i
+ j
))))
420 if (constantp
[j
] != bundle_constants
[i
+ j
])
426 /* Select the place where existing bytes can be
427 * reused so we leave empty slots to others
429 if (j
== type_size
&&
430 (reuse_bytes
> best_reuse_bytes
|| best_place
< 0)) {
431 best_reuse_bytes
= reuse_bytes
;
437 /* This component couldn't fit in the remaining constant slot,
438 * no need check the remaining components, bail out now
443 memcpy(&bundle_constants
[i
], constantp
, type_size
);
444 bundle_constant_mask
|= type_mask
<< best_place
;
445 comp_mapping
[comp
] = best_place
/ type_size
;
448 /* If non-destructive, we're done */
452 /* Otherwise update the constant_mask and constant values */
453 pred
->constant_mask
= bundle_constant_mask
;
454 memcpy(pred
->constants
, bundle_constants
, 16);
456 /* Use comp_mapping as a swizzle */
457 mir_foreach_src(ins
, s
) {
458 if (ins
->src
[s
] == r_constant
)
459 mir_compose_swizzle(ins
->swizzle
[s
], comp_mapping
, ins
->swizzle
[s
]);
465 static midgard_instruction
*
466 mir_choose_instruction(
467 midgard_instruction
**instructions
,
468 BITSET_WORD
*worklist
, unsigned count
,
469 struct midgard_predicate
*predicate
)
471 /* Parse the predicate */
472 unsigned tag
= predicate
->tag
;
473 bool alu
= tag
== TAG_ALU_4
;
474 unsigned unit
= predicate
->unit
;
475 bool branch
= alu
&& (unit
== ALU_ENAB_BR_COMPACT
);
476 bool scalar
= (unit
!= ~0) && (unit
& UNITS_SCALAR
);
477 bool no_cond
= predicate
->no_cond
;
479 unsigned mask
= predicate
->mask
;
480 unsigned dest
= predicate
->dest
;
481 bool needs_dest
= mask
& 0xF;
483 /* Iterate to find the best instruction satisfying the predicate */
487 signed best_index
= -1;
488 bool best_conditional
= false;
490 /* Enforce a simple metric limiting distance to keep down register
491 * pressure. TOOD: replace with liveness tracking for much better
494 unsigned max_active
= 0;
495 unsigned max_distance
= 6;
497 BITSET_FOREACH_SET(i
, tmp
, worklist
, count
) {
498 max_active
= MAX2(max_active
, i
);
501 BITSET_FOREACH_SET(i
, tmp
, worklist
, count
) {
502 if ((max_active
- i
) >= max_distance
)
505 if (tag
!= ~0 && instructions
[i
]->type
!= tag
)
508 if (predicate
->exclude
!= ~0 && instructions
[i
]->dest
== predicate
->exclude
)
511 if (alu
&& !branch
&& !(alu_opcode_props
[instructions
[i
]->alu
.op
].props
& unit
))
514 if (branch
&& !instructions
[i
]->compact_branch
)
517 if (alu
&& scalar
&& !mir_is_scalar(instructions
[i
]))
520 if (alu
&& !mir_adjust_constants(instructions
[i
], predicate
, false))
523 if (needs_dest
&& instructions
[i
]->dest
!= dest
)
526 if (mask
&& ((~instructions
[i
]->mask
) & mask
))
529 bool conditional
= alu
&& !branch
&& OP_IS_CSEL(instructions
[i
]->alu
.op
);
530 conditional
|= (branch
&& instructions
[i
]->branch
.conditional
);
532 if (conditional
&& no_cond
)
535 /* Simulate in-order scheduling */
536 if ((signed) i
< best_index
)
540 best_conditional
= conditional
;
544 /* Did we find anything? */
549 /* If we found something, remove it from the worklist */
550 assert(best_index
< count
);
552 if (predicate
->destructive
) {
553 BITSET_CLEAR(worklist
, best_index
);
556 mir_adjust_constants(instructions
[best_index
], predicate
, true);
558 /* Once we schedule a conditional, we can't again */
559 predicate
->no_cond
|= best_conditional
;
562 return instructions
[best_index
];
565 /* Still, we don't choose instructions in a vacuum. We need a way to choose the
566 * best bundle type (ALU, load/store, texture). Nondestructive. */
570 midgard_instruction
**instructions
,
571 BITSET_WORD
*worklist
, unsigned count
)
573 /* At the moment, our algorithm is very simple - use the bundle of the
574 * best instruction, regardless of what else could be scheduled
575 * alongside it. This is not optimal but it works okay for in-order */
577 struct midgard_predicate predicate
= {
579 .destructive
= false,
583 midgard_instruction
*chosen
= mir_choose_instruction(instructions
, worklist
, count
, &predicate
);
591 /* We want to choose an ALU instruction filling a given unit */
593 mir_choose_alu(midgard_instruction
**slot
,
594 midgard_instruction
**instructions
,
595 BITSET_WORD
*worklist
, unsigned len
,
596 struct midgard_predicate
*predicate
,
599 /* Did we already schedule to this slot? */
603 /* Try to schedule something, if not */
604 predicate
->unit
= unit
;
605 *slot
= mir_choose_instruction(instructions
, worklist
, len
, predicate
);
607 /* Store unit upon scheduling */
608 if (*slot
&& !((*slot
)->compact_branch
))
609 (*slot
)->unit
= unit
;
612 /* When we are scheduling a branch/csel, we need the consumed condition in the
613 * same block as a pipeline register. There are two options to enable this:
615 * - Move the conditional into the bundle. Preferred, but only works if the
616 * conditional is used only once and is from this block.
617 * - Copy the conditional.
619 * We search for the conditional. If it's in this block, single-use, and
620 * without embedded constants, we schedule it immediately. Otherwise, we
621 * schedule a move for it.
623 * mir_comparison_mobile is a helper to find the moveable condition.
627 mir_comparison_mobile(
628 compiler_context
*ctx
,
629 midgard_instruction
**instructions
,
630 struct midgard_predicate
*predicate
,
634 if (!mir_single_use(ctx
, cond
))
639 for (unsigned i
= 0; i
< count
; ++i
) {
640 if (instructions
[i
]->dest
!= cond
)
643 /* Must fit in an ALU bundle */
644 if (instructions
[i
]->type
!= TAG_ALU_4
)
647 /* If it would itself require a condition, that's recursive */
648 if (OP_IS_CSEL(instructions
[i
]->alu
.op
))
651 /* We'll need to rewrite to .w but that doesn't work for vector
652 * ops that don't replicate (ball/bany), so bail there */
654 if (GET_CHANNEL_COUNT(alu_opcode_props
[instructions
[i
]->alu
.op
].props
))
657 /* Ensure it will fit with constants */
659 if (!mir_adjust_constants(instructions
[i
], predicate
, false))
662 /* Ensure it is written only once */
670 /* Inject constants now that we are sure we want to */
672 mir_adjust_constants(instructions
[ret
], predicate
, true);
677 /* Using the information about the moveable conditional itself, we either pop
678 * that condition off the worklist for use now, or create a move to
679 * artificially schedule instead as a fallback */
681 static midgard_instruction
*
682 mir_schedule_comparison(
683 compiler_context
*ctx
,
684 midgard_instruction
**instructions
,
685 struct midgard_predicate
*predicate
,
686 BITSET_WORD
*worklist
, unsigned count
,
687 unsigned cond
, bool vector
, unsigned *swizzle
,
688 midgard_instruction
*user
)
690 /* TODO: swizzle when scheduling */
692 (!vector
&& (swizzle
[0] == 0)) ?
693 mir_comparison_mobile(ctx
, instructions
, predicate
, count
, cond
) : ~0;
695 /* If we can, schedule the condition immediately */
696 if ((comp_i
!= ~0) && BITSET_TEST(worklist
, comp_i
)) {
697 assert(comp_i
< count
);
698 BITSET_CLEAR(worklist
, comp_i
);
699 return instructions
[comp_i
];
702 /* Otherwise, we insert a move */
704 midgard_instruction mov
= v_mov(cond
, cond
);
705 mov
.mask
= vector
? 0xF : 0x1;
706 memcpy(mov
.swizzle
[1], swizzle
, sizeof(mov
.swizzle
[1]));
708 return mir_insert_instruction_before(ctx
, user
, mov
);
711 /* Most generally, we need instructions writing to r31 in the appropriate
714 static midgard_instruction
*
715 mir_schedule_condition(compiler_context
*ctx
,
716 struct midgard_predicate
*predicate
,
717 BITSET_WORD
*worklist
, unsigned count
,
718 midgard_instruction
**instructions
,
719 midgard_instruction
*last
)
721 /* For a branch, the condition is the only argument; for csel, third */
722 bool branch
= last
->compact_branch
;
723 unsigned condition_index
= branch
? 0 : 2;
725 /* csel_v is vector; otherwise, conditions are scalar */
726 bool vector
= !branch
&& OP_IS_CSEL_V(last
->alu
.op
);
728 /* Grab the conditional instruction */
730 midgard_instruction
*cond
= mir_schedule_comparison(
731 ctx
, instructions
, predicate
, worklist
, count
, last
->src
[condition_index
],
732 vector
, last
->swizzle
[2], last
);
734 /* We have exclusive reign over this (possibly move) conditional
735 * instruction. We can rewrite into a pipeline conditional register */
737 predicate
->exclude
= cond
->dest
;
738 cond
->dest
= SSA_FIXED_REGISTER(31);
741 cond
->mask
= (1 << COMPONENT_W
);
743 mir_foreach_src(cond
, s
) {
744 if (cond
->src
[s
] == ~0)
747 for (unsigned q
= 0; q
< 4; ++q
)
748 cond
->swizzle
[s
][q
+ COMPONENT_W
] = cond
->swizzle
[s
][q
];
752 /* Schedule the unit: csel is always in the latter pipeline, so a csel
753 * condition must be in the former pipeline stage (vmul/sadd),
754 * depending on scalar/vector of the instruction itself. A branch must
755 * be written from the latter pipeline stage and a branch condition is
756 * always scalar, so it is always in smul (exception: ball/bany, which
760 cond
->unit
= UNIT_SMUL
;
762 cond
->unit
= vector
? UNIT_VMUL
: UNIT_SADD
;
767 /* Schedules a single bundle of the given type */
769 static midgard_bundle
770 mir_schedule_texture(
771 midgard_instruction
**instructions
,
772 BITSET_WORD
*worklist
, unsigned len
)
774 struct midgard_predicate predicate
= {
775 .tag
= TAG_TEXTURE_4
,
780 midgard_instruction
*ins
=
781 mir_choose_instruction(instructions
, worklist
, len
, &predicate
);
783 mir_update_worklist(worklist
, len
, instructions
, ins
);
785 struct midgard_bundle out
= {
786 .tag
= TAG_TEXTURE_4
,
787 .instruction_count
= 1,
788 .instructions
= { ins
}
794 static midgard_bundle
796 midgard_instruction
**instructions
,
797 BITSET_WORD
*worklist
, unsigned len
)
799 struct midgard_predicate predicate
= {
800 .tag
= TAG_LOAD_STORE_4
,
805 /* Try to pick two load/store ops. Second not gauranteed to exist */
807 midgard_instruction
*ins
=
808 mir_choose_instruction(instructions
, worklist
, len
, &predicate
);
810 midgard_instruction
*pair
=
811 mir_choose_instruction(instructions
, worklist
, len
, &predicate
);
813 struct midgard_bundle out
= {
814 .tag
= TAG_LOAD_STORE_4
,
815 .instruction_count
= pair
? 2 : 1,
816 .instructions
= { ins
, pair
}
819 /* We have to update the worklist atomically, since the two
820 * instructions run concurrently (TODO: verify it's not pipelined) */
822 mir_update_worklist(worklist
, len
, instructions
, ins
);
823 mir_update_worklist(worklist
, len
, instructions
, pair
);
828 static midgard_bundle
830 compiler_context
*ctx
,
831 midgard_instruction
**instructions
,
832 BITSET_WORD
*worklist
, unsigned len
)
834 struct midgard_bundle bundle
= {};
836 unsigned bytes_emitted
= sizeof(bundle
.control
);
838 struct midgard_predicate predicate
= {
842 .constants
= &bundle
.constants
845 midgard_instruction
*vmul
= NULL
;
846 midgard_instruction
*vadd
= NULL
;
847 midgard_instruction
*vlut
= NULL
;
848 midgard_instruction
*smul
= NULL
;
849 midgard_instruction
*sadd
= NULL
;
850 midgard_instruction
*branch
= NULL
;
852 mir_choose_alu(&branch
, instructions
, worklist
, len
, &predicate
, ALU_ENAB_BR_COMPACT
);
853 mir_update_worklist(worklist
, len
, instructions
, branch
);
854 bool writeout
= branch
&& branch
->writeout
;
856 if (branch
&& branch
->branch
.conditional
) {
857 midgard_instruction
*cond
= mir_schedule_condition(ctx
, &predicate
, worklist
, len
, instructions
, branch
);
859 if (cond
->unit
== UNIT_VADD
)
861 else if (cond
->unit
== UNIT_SMUL
)
864 unreachable("Bad condition");
867 mir_choose_alu(&smul
, instructions
, worklist
, len
, &predicate
, UNIT_SMUL
);
870 mir_choose_alu(&vlut
, instructions
, worklist
, len
, &predicate
, UNIT_VLUT
);
874 bundle
.last_writeout
= branch
->last_writeout
;
876 midgard_instruction add
= v_mov(~0, make_compiler_temp(ctx
));
878 if (!ctx
->is_blend
) {
879 add
.alu
.op
= midgard_alu_op_iadd
;
880 add
.src
[0] = SSA_FIXED_REGISTER(31);
882 for (unsigned c
= 0; c
< 16; ++c
)
883 add
.swizzle
[0][c
] = COMPONENT_X
;
885 add
.has_inline_constant
= true;
886 add
.inline_constant
= 0;
888 add
.src
[1] = SSA_FIXED_REGISTER(1);
890 for (unsigned c
= 0; c
< 16; ++c
)
891 add
.swizzle
[1][c
] = COMPONENT_W
;
894 vadd
= mem_dup(&add
, sizeof(midgard_instruction
));
896 vadd
->unit
= UNIT_VADD
;
898 branch
->src
[2] = add
.dest
;
901 mir_choose_alu(&vadd
, instructions
, worklist
, len
, &predicate
, UNIT_VADD
);
903 mir_update_worklist(worklist
, len
, instructions
, vlut
);
904 mir_update_worklist(worklist
, len
, instructions
, vadd
);
905 mir_update_worklist(worklist
, len
, instructions
, smul
);
907 bool vadd_csel
= vadd
&& OP_IS_CSEL(vadd
->alu
.op
);
908 bool smul_csel
= smul
&& OP_IS_CSEL(smul
->alu
.op
);
910 if (vadd_csel
|| smul_csel
) {
911 midgard_instruction
*ins
= vadd_csel
? vadd
: smul
;
912 midgard_instruction
*cond
= mir_schedule_condition(ctx
, &predicate
, worklist
, len
, instructions
, ins
);
914 if (cond
->unit
== UNIT_VMUL
)
916 else if (cond
->unit
== UNIT_SADD
)
919 unreachable("Bad condition");
922 /* If we have a render target reference, schedule a move for it */
924 if (branch
&& branch
->writeout
&& (branch
->constants
.u32
[0] || ctx
->is_blend
)) {
925 midgard_instruction mov
= v_mov(~0, make_compiler_temp(ctx
));
926 sadd
= mem_dup(&mov
, sizeof(midgard_instruction
));
927 sadd
->unit
= UNIT_SADD
;
929 sadd
->has_inline_constant
= true;
930 sadd
->inline_constant
= branch
->constants
.u32
[0];
931 branch
->src
[1] = mov
.dest
;
932 /* TODO: Don't leak */
935 /* Stage 2, let's schedule sadd before vmul for writeout */
936 mir_choose_alu(&sadd
, instructions
, worklist
, len
, &predicate
, UNIT_SADD
);
938 /* Check if writeout reads its own register */
940 if (branch
&& branch
->writeout
) {
941 midgard_instruction
*stages
[] = { sadd
, vadd
, smul
};
942 unsigned src
= (branch
->src
[0] == ~0) ? SSA_FIXED_REGISTER(0) : branch
->src
[0];
943 unsigned writeout_mask
= 0x0;
944 bool bad_writeout
= false;
946 for (unsigned i
= 0; i
< ARRAY_SIZE(stages
); ++i
) {
950 if (stages
[i
]->dest
!= src
)
953 writeout_mask
|= stages
[i
]->mask
;
954 bad_writeout
|= mir_has_arg(stages
[i
], branch
->src
[0]);
957 /* It's possible we'll be able to schedule something into vmul
958 * to fill r0. Let's peak into the future, trying to schedule
959 * vmul specially that way. */
961 if (!bad_writeout
&& writeout_mask
!= 0xF) {
962 predicate
.unit
= UNIT_VMUL
;
963 predicate
.dest
= src
;
964 predicate
.mask
= writeout_mask
^ 0xF;
966 struct midgard_instruction
*peaked
=
967 mir_choose_instruction(instructions
, worklist
, len
, &predicate
);
971 vmul
->unit
= UNIT_VMUL
;
972 writeout_mask
|= predicate
.mask
;
973 assert(writeout_mask
== 0xF);
977 predicate
.dest
= predicate
.mask
= 0;
980 /* Finally, add a move if necessary */
981 if (bad_writeout
|| writeout_mask
!= 0xF) {
982 unsigned temp
= (branch
->src
[0] == ~0) ? SSA_FIXED_REGISTER(0) : make_compiler_temp(ctx
);
983 midgard_instruction mov
= v_mov(src
, temp
);
984 vmul
= mem_dup(&mov
, sizeof(midgard_instruction
));
985 vmul
->unit
= UNIT_VMUL
;
986 vmul
->mask
= 0xF ^ writeout_mask
;
987 /* TODO: Don't leak */
989 /* Rewrite to use our temp */
991 for (unsigned i
= 0; i
< ARRAY_SIZE(stages
); ++i
) {
993 mir_rewrite_index_dst_single(stages
[i
], src
, temp
);
996 mir_rewrite_index_src_single(branch
, src
, temp
);
1000 mir_choose_alu(&vmul
, instructions
, worklist
, len
, &predicate
, UNIT_VMUL
);
1002 mir_update_worklist(worklist
, len
, instructions
, vmul
);
1003 mir_update_worklist(worklist
, len
, instructions
, sadd
);
1005 bundle
.has_blend_constant
= predicate
.blend_constant
;
1006 bundle
.has_embedded_constants
= predicate
.constant_mask
!= 0;
1008 unsigned padding
= 0;
1010 /* Now that we have finished scheduling, build up the bundle */
1011 midgard_instruction
*stages
[] = { vmul
, sadd
, vadd
, smul
, vlut
, branch
};
1013 for (unsigned i
= 0; i
< ARRAY_SIZE(stages
); ++i
) {
1015 bundle
.control
|= stages
[i
]->unit
;
1016 bytes_emitted
+= bytes_for_instruction(stages
[i
]);
1017 bundle
.instructions
[bundle
.instruction_count
++] = stages
[i
];
1021 /* Pad ALU op to nearest word */
1023 if (bytes_emitted
& 15) {
1024 padding
= 16 - (bytes_emitted
& 15);
1025 bytes_emitted
+= padding
;
1028 /* Constants must always be quadwords */
1029 if (bundle
.has_embedded_constants
)
1030 bytes_emitted
+= 16;
1032 /* Size ALU instruction for tag */
1033 bundle
.tag
= (TAG_ALU_4
) + (bytes_emitted
/ 16) - 1;
1035 /* MRT capable GPUs use a special writeout procedure */
1036 if (writeout
&& !(ctx
->quirks
& MIDGARD_NO_UPPER_ALU
))
1039 bundle
.padding
= padding
;
1040 bundle
.control
|= bundle
.tag
;
1045 /* Schedule a single block by iterating its instruction to create bundles.
1046 * While we go, tally about the bundle sizes to compute the block size. */
1050 schedule_block(compiler_context
*ctx
, midgard_block
*block
)
1052 /* Copy list to dynamic array */
1054 midgard_instruction
**instructions
= flatten_mir(block
, &len
);
1059 /* Calculate dependencies and initial worklist */
1060 unsigned node_count
= ctx
->temp_count
+ 1;
1061 mir_create_dependency_graph(instructions
, len
, node_count
);
1063 /* Allocate the worklist */
1064 size_t sz
= BITSET_WORDS(len
) * sizeof(BITSET_WORD
);
1065 BITSET_WORD
*worklist
= calloc(sz
, 1);
1066 mir_initialize_worklist(worklist
, instructions
, len
);
1068 struct util_dynarray bundles
;
1069 util_dynarray_init(&bundles
, NULL
);
1071 block
->quadword_count
= 0;
1072 unsigned blend_offset
= 0;
1075 unsigned tag
= mir_choose_bundle(instructions
, worklist
, len
);
1076 midgard_bundle bundle
;
1078 if (tag
== TAG_TEXTURE_4
)
1079 bundle
= mir_schedule_texture(instructions
, worklist
, len
);
1080 else if (tag
== TAG_LOAD_STORE_4
)
1081 bundle
= mir_schedule_ldst(instructions
, worklist
, len
);
1082 else if (tag
== TAG_ALU_4
)
1083 bundle
= mir_schedule_alu(ctx
, instructions
, worklist
, len
);
1087 util_dynarray_append(&bundles
, midgard_bundle
, bundle
);
1089 if (bundle
.has_blend_constant
)
1090 blend_offset
= block
->quadword_count
;
1092 block
->quadword_count
+= midgard_word_size
[bundle
.tag
];
1095 /* We emitted bundles backwards; copy into the block in reverse-order */
1097 util_dynarray_init(&block
->bundles
, NULL
);
1098 util_dynarray_foreach_reverse(&bundles
, midgard_bundle
, bundle
) {
1099 util_dynarray_append(&block
->bundles
, midgard_bundle
, *bundle
);
1102 /* Blend constant was backwards as well. blend_offset if set is
1103 * strictly positive, as an offset of zero would imply constants before
1104 * any instructions which is invalid in Midgard. TODO: blend constants
1105 * are broken if you spill since then quadword_count becomes invalid
1109 ctx
->blend_constant_offset
= ((ctx
->quadword_count
+ block
->quadword_count
) - blend_offset
- 1) * 0x10;
1111 block
->is_scheduled
= true;
1112 ctx
->quadword_count
+= block
->quadword_count
;
1114 /* Reorder instructions to match bundled. First remove existing
1115 * instructions and then recreate the list */
1117 mir_foreach_instr_in_block_safe(block
, ins
) {
1118 list_del(&ins
->link
);
1121 mir_foreach_instr_in_block_scheduled_rev(block
, ins
) {
1122 list_add(&ins
->link
, &block
->instructions
);
1125 free(instructions
); /* Allocated by flatten_mir() */
1130 midgard_schedule_program(compiler_context
*ctx
)
1132 midgard_promote_uniforms(ctx
);
1134 /* Must be lowered right before scheduling */
1135 mir_squeeze_index(ctx
);
1136 mir_lower_special_reads(ctx
);
1137 mir_squeeze_index(ctx
);
1139 /* Lowering can introduce some dead moves */
1141 mir_foreach_block(ctx
, block
) {
1142 midgard_opt_dead_move_eliminate(ctx
, block
);
1143 schedule_block(ctx
, block
);