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pan/midgard: Fold ssa_args into midgard_instruction
[mesa.git] / src / panfrost / midgard / midgard_schedule.c
1 /*
2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 */
23
24 #include "compiler.h"
25 #include "midgard_ops.h"
26 #include "util/u_memory.h"
27 #include "util/register_allocate.h"
28
29 /* Create a mask of accessed components from a swizzle to figure out vector
30 * dependencies */
31
32 static unsigned
33 swizzle_to_access_mask(unsigned swizzle)
34 {
35 unsigned component_mask = 0;
36
37 for (int i = 0; i < 4; ++i) {
38 unsigned c = (swizzle >> (2 * i)) & 3;
39 component_mask |= (1 << c);
40 }
41
42 return component_mask;
43 }
44
45 /* Does the mask cover more than a scalar? */
46
47 static bool
48 is_single_component_mask(unsigned mask)
49 {
50 int components = 0;
51
52 for (int c = 0; c < 8; ++c) {
53 if (mask & (1 << c))
54 components++;
55 }
56
57 return components == 1;
58 }
59
60 /* Checks for an SSA data hazard between two adjacent instructions, keeping in
61 * mind that we are a vector architecture and we can write to different
62 * components simultaneously */
63
64 static bool
65 can_run_concurrent_ssa(midgard_instruction *first, midgard_instruction *second)
66 {
67 /* Writeout has its own rules anyway */
68 if (first->compact_branch || second->compact_branch)
69 return true;
70
71 /* Each instruction reads some registers and writes to a register. See
72 * where the first writes */
73
74 int source = first->dest;
75 int source_mask = first->mask;
76
77 /* As long as the second doesn't read from the first, we're okay */
78 for (unsigned i = 0; i < ARRAY_SIZE(second->src); ++i) {
79 if (second->src[i] != source)
80 continue;
81
82 if (first->type != TAG_ALU_4)
83 return false;
84
85 /* Figure out which components we just read from */
86
87 int q = (i == 0) ? second->alu.src1 : second->alu.src2;
88 midgard_vector_alu_src *m = (midgard_vector_alu_src *) &q;
89
90 /* Check if there are components in common, and fail if so */
91 if (swizzle_to_access_mask(m->swizzle) & source_mask)
92 return false;
93 }
94
95 /* Otherwise, it's safe in that regard. Another data hazard is both
96 * writing to the same place, of course */
97
98 if (second->dest == source) {
99 /* ...but only if the components overlap */
100
101 if (second->mask & source_mask)
102 return false;
103 }
104
105 /* ...That's it */
106 return true;
107 }
108
109 static bool
110 midgard_has_hazard(
111 midgard_instruction **segment, unsigned segment_size,
112 midgard_instruction *ains)
113 {
114 for (int s = 0; s < segment_size; ++s)
115 if (!can_run_concurrent_ssa(segment[s], ains))
116 return true;
117
118 return false;
119
120
121 }
122
123 /* Fragment writeout (of r0) is allowed when:
124 *
125 * - All components of r0 are written in the bundle
126 * - No components of r0 are written in VLUT
127 * - Non-pipelined dependencies of r0 are not written in the bundle
128 *
129 * This function checks if these requirements are satisfied given the content
130 * of a scheduled bundle.
131 */
132
133 static bool
134 can_writeout_fragment(compiler_context *ctx, midgard_instruction **bundle, unsigned count, unsigned node_count)
135 {
136 /* First scan for which components of r0 are written out. Initially
137 * none are written */
138
139 uint8_t r0_written_mask = 0x0;
140
141 /* Simultaneously we scan for the set of dependencies */
142
143 size_t sz = sizeof(BITSET_WORD) * BITSET_WORDS(node_count);
144 BITSET_WORD *dependencies = alloca(sz);
145 memset(dependencies, 0, sz);
146
147 for (unsigned i = 0; i < count; ++i) {
148 midgard_instruction *ins = bundle[i];
149
150 if (ins->dest != SSA_FIXED_REGISTER(0))
151 continue;
152
153 /* Record written out mask */
154 r0_written_mask |= ins->mask;
155
156 /* Record dependencies, but only if they won't become pipeline
157 * registers. We know we can't be live after this, because
158 * we're writeout at the very end of the shader. So check if
159 * they were written before us. */
160
161 unsigned src0 = ins->src[0];
162 unsigned src1 = ins->src[1];
163
164 if (!mir_is_written_before(ctx, bundle[0], src0))
165 src0 = ~0;
166
167 if (!mir_is_written_before(ctx, bundle[0], src1))
168 src1 = ~0;
169
170 if (src0 < node_count)
171 BITSET_SET(dependencies, src0);
172
173 if (src1 < node_count)
174 BITSET_SET(dependencies, src1);
175
176 /* Requirement 2 */
177 if (ins->unit == UNIT_VLUT)
178 return false;
179 }
180
181 /* Requirement 1 */
182 if ((r0_written_mask & 0xF) != 0xF)
183 return false;
184
185 /* Requirement 3 */
186
187 for (unsigned i = 0; i < count; ++i) {
188 unsigned dest = bundle[i]->dest;
189
190 if (dest < node_count && BITSET_TEST(dependencies, dest))
191 return false;
192 }
193
194 /* Otherwise, we're good to go */
195 return true;
196 }
197
198 /* Schedules, but does not emit, a single basic block. After scheduling, the
199 * final tag and size of the block are known, which are necessary for branching
200 * */
201
202 static midgard_bundle
203 schedule_bundle(compiler_context *ctx, midgard_block *block, midgard_instruction *ins, int *skip)
204 {
205 int instructions_emitted = 0, packed_idx = 0;
206 midgard_bundle bundle = { 0 };
207
208 midgard_instruction *scheduled[5] = { NULL };
209
210 uint8_t tag = ins->type;
211
212 /* Default to the instruction's tag */
213 bundle.tag = tag;
214
215 switch (ins->type) {
216 case TAG_ALU_4: {
217 uint32_t control = 0;
218 size_t bytes_emitted = sizeof(control);
219
220 /* TODO: Constant combining */
221 int index = 0, last_unit = 0;
222
223 /* Previous instructions, for the purpose of parallelism */
224 midgard_instruction *segment[4] = {0};
225 int segment_size = 0;
226
227 instructions_emitted = -1;
228 midgard_instruction *pins = ins;
229
230 unsigned constant_count = 0;
231
232 for (;;) {
233 midgard_instruction *ains = pins;
234
235 /* Advance instruction pointer */
236 if (index) {
237 ains = mir_next_op(pins);
238 pins = ains;
239 }
240
241 /* Out-of-work condition */
242 if ((struct list_head *) ains == &block->instructions)
243 break;
244
245 /* Ensure that the chain can continue */
246 if (ains->type != TAG_ALU_4) break;
247
248 /* If there's already something in the bundle and we
249 * have weird scheduler constraints, break now */
250 if (ains->precede_break && index) break;
251
252 /* According to the presentation "The ARM
253 * Mali-T880 Mobile GPU" from HotChips 27,
254 * there are two pipeline stages. Branching
255 * position determined experimentally. Lines
256 * are executed in parallel:
257 *
258 * [ VMUL ] [ SADD ]
259 * [ VADD ] [ SMUL ] [ LUT ] [ BRANCH ]
260 *
261 * Verify that there are no ordering dependencies here.
262 *
263 * TODO: Allow for parallelism!!!
264 */
265
266 /* Pick a unit for it if it doesn't force a particular unit */
267
268 int unit = ains->unit;
269
270 if (!unit) {
271 int op = ains->alu.op;
272 int units = alu_opcode_props[op].props;
273
274 bool scalarable = units & UNITS_SCALAR;
275 bool could_scalar = is_single_component_mask(ains->mask);
276
277 /* Only 16/32-bit can run on a scalar unit */
278 could_scalar &= ains->alu.reg_mode != midgard_reg_mode_8;
279 could_scalar &= ains->alu.reg_mode != midgard_reg_mode_64;
280 could_scalar &= ains->alu.dest_override == midgard_dest_override_none;
281
282 if (ains->alu.reg_mode == midgard_reg_mode_16) {
283 /* If we're running in 16-bit mode, we
284 * can't have any 8-bit sources on the
285 * scalar unit (since the scalar unit
286 * doesn't understand 8-bit) */
287
288 midgard_vector_alu_src s1 =
289 vector_alu_from_unsigned(ains->alu.src1);
290
291 could_scalar &= !s1.half;
292
293 midgard_vector_alu_src s2 =
294 vector_alu_from_unsigned(ains->alu.src2);
295
296 could_scalar &= !s2.half;
297 }
298
299 bool scalar = could_scalar && scalarable;
300
301 /* TODO: Check ahead-of-time for other scalar
302 * hazards that otherwise get aborted out */
303
304 if (scalar)
305 assert(units & UNITS_SCALAR);
306
307 if (!scalar) {
308 if (last_unit >= UNIT_VADD) {
309 if (units & UNIT_VLUT)
310 unit = UNIT_VLUT;
311 else
312 break;
313 } else {
314 if ((units & UNIT_VMUL) && last_unit < UNIT_VMUL)
315 unit = UNIT_VMUL;
316 else if ((units & UNIT_VADD) && !(control & UNIT_VADD))
317 unit = UNIT_VADD;
318 else if (units & UNIT_VLUT)
319 unit = UNIT_VLUT;
320 else
321 break;
322 }
323 } else {
324 if (last_unit >= UNIT_VADD) {
325 if ((units & UNIT_SMUL) && !(control & UNIT_SMUL))
326 unit = UNIT_SMUL;
327 else if (units & UNIT_VLUT)
328 unit = UNIT_VLUT;
329 else
330 break;
331 } else {
332 if ((units & UNIT_VMUL) && (last_unit < UNIT_VMUL))
333 unit = UNIT_VMUL;
334 else if ((units & UNIT_SADD) && !(control & UNIT_SADD) && !midgard_has_hazard(segment, segment_size, ains))
335 unit = UNIT_SADD;
336 else if (units & UNIT_VADD)
337 unit = UNIT_VADD;
338 else if (units & UNIT_SMUL)
339 unit = UNIT_SMUL;
340 else if (units & UNIT_VLUT)
341 unit = UNIT_VLUT;
342 else
343 break;
344 }
345 }
346
347 assert(unit & units);
348 }
349
350 /* Late unit check, this time for encoding (not parallelism) */
351 if (unit <= last_unit) break;
352
353 /* Clear the segment */
354 if (last_unit < UNIT_VADD && unit >= UNIT_VADD)
355 segment_size = 0;
356
357 if (midgard_has_hazard(segment, segment_size, ains))
358 break;
359
360 /* We're good to go -- emit the instruction */
361 ains->unit = unit;
362
363 segment[segment_size++] = ains;
364
365 /* We try to reuse constants if possible, by adjusting
366 * the swizzle */
367
368 if (ains->has_blend_constant) {
369 /* Everything conflicts with the blend constant */
370 if (bundle.has_embedded_constants)
371 break;
372
373 bundle.has_blend_constant = 1;
374 bundle.has_embedded_constants = 1;
375 } else if (ains->has_constants && ains->alu.reg_mode == midgard_reg_mode_16) {
376 /* TODO: DRY with the analysis pass */
377
378 if (bundle.has_blend_constant)
379 break;
380
381 if (constant_count)
382 break;
383
384 /* TODO: Fix packing XXX */
385 uint16_t *bundles = (uint16_t *) bundle.constants;
386 uint32_t *constants = (uint32_t *) ains->constants;
387
388 /* Copy them wholesale */
389 for (unsigned i = 0; i < 4; ++i)
390 bundles[i] = constants[i];
391
392 bundle.has_embedded_constants = true;
393 constant_count = 4;
394 } else if (ains->has_constants) {
395 /* By definition, blend constants conflict with
396 * everything, so if there are already
397 * constants we break the bundle *now* */
398
399 if (bundle.has_blend_constant)
400 break;
401
402 /* For anything but blend constants, we can do
403 * proper analysis, however */
404
405 /* TODO: Mask by which are used */
406 uint32_t *constants = (uint32_t *) ains->constants;
407 uint32_t *bundles = (uint32_t *) bundle.constants;
408
409 uint32_t indices[4] = { 0 };
410 bool break_bundle = false;
411
412 for (unsigned i = 0; i < 4; ++i) {
413 uint32_t cons = constants[i];
414 bool constant_found = false;
415
416 /* Search for the constant */
417 for (unsigned j = 0; j < constant_count; ++j) {
418 if (bundles[j] != cons)
419 continue;
420
421 /* We found it, reuse */
422 indices[i] = j;
423 constant_found = true;
424 break;
425 }
426
427 if (constant_found)
428 continue;
429
430 /* We didn't find it, so allocate it */
431 unsigned idx = constant_count++;
432
433 if (idx >= 4) {
434 /* Uh-oh, out of space */
435 break_bundle = true;
436 break;
437 }
438
439 /* We have space, copy it in! */
440 bundles[idx] = cons;
441 indices[i] = idx;
442 }
443
444 if (break_bundle)
445 break;
446
447 /* Cool, we have it in. So use indices as a
448 * swizzle */
449
450 unsigned swizzle = SWIZZLE_FROM_ARRAY(indices);
451 unsigned r_constant = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
452
453 if (ains->src[0] == r_constant)
454 ains->alu.src1 = vector_alu_apply_swizzle(ains->alu.src1, swizzle);
455
456 if (ains->src[1] == r_constant)
457 ains->alu.src2 = vector_alu_apply_swizzle(ains->alu.src2, swizzle);
458
459 bundle.has_embedded_constants = true;
460 }
461
462 if (ains->unit & UNITS_ANY_VECTOR) {
463 bytes_emitted += sizeof(midgard_reg_info);
464 bytes_emitted += sizeof(midgard_vector_alu);
465 } else if (ains->compact_branch) {
466 /* All of r0 has to be written out along with
467 * the branch writeout */
468
469 if (ains->writeout && !can_writeout_fragment(ctx, scheduled, index, ctx->temp_count)) {
470 /* We only work on full moves
471 * at the beginning. We could
472 * probably do better */
473 if (index != 0)
474 break;
475
476 /* Inject a move */
477 midgard_instruction ins = v_mov(0, blank_alu_src, SSA_FIXED_REGISTER(0));
478 ins.unit = UNIT_VMUL;
479 control |= ins.unit;
480
481 /* TODO don't leak */
482 midgard_instruction *move =
483 mem_dup(&ins, sizeof(midgard_instruction));
484 bytes_emitted += sizeof(midgard_reg_info);
485 bytes_emitted += sizeof(midgard_vector_alu);
486 bundle.instructions[packed_idx++] = move;
487 }
488
489 if (ains->unit == ALU_ENAB_BRANCH) {
490 bytes_emitted += sizeof(midgard_branch_extended);
491 } else {
492 bytes_emitted += sizeof(ains->br_compact);
493 }
494 } else {
495 bytes_emitted += sizeof(midgard_reg_info);
496 bytes_emitted += sizeof(midgard_scalar_alu);
497 }
498
499 /* Defer marking until after writing to allow for break */
500 scheduled[index] = ains;
501 control |= ains->unit;
502 last_unit = ains->unit;
503 ++instructions_emitted;
504 ++index;
505 }
506
507 int padding = 0;
508
509 /* Pad ALU op to nearest word */
510
511 if (bytes_emitted & 15) {
512 padding = 16 - (bytes_emitted & 15);
513 bytes_emitted += padding;
514 }
515
516 /* Constants must always be quadwords */
517 if (bundle.has_embedded_constants)
518 bytes_emitted += 16;
519
520 /* Size ALU instruction for tag */
521 bundle.tag = (TAG_ALU_4) + (bytes_emitted / 16) - 1;
522 bundle.padding = padding;
523 bundle.control = bundle.tag | control;
524
525 break;
526 }
527
528 case TAG_LOAD_STORE_4: {
529 /* Load store instructions have two words at once. If
530 * we only have one queued up, we need to NOP pad.
531 * Otherwise, we store both in succession to save space
532 * and cycles -- letting them go in parallel -- skip
533 * the next. The usefulness of this optimisation is
534 * greatly dependent on the quality of the instruction
535 * scheduler.
536 */
537
538 midgard_instruction *next_op = mir_next_op(ins);
539
540 if ((struct list_head *) next_op != &block->instructions && next_op->type == TAG_LOAD_STORE_4) {
541 /* TODO: Concurrency check */
542 instructions_emitted++;
543 }
544
545 break;
546 }
547
548 case TAG_TEXTURE_4: {
549 /* Which tag we use depends on the shader stage */
550 bool in_frag = ctx->stage == MESA_SHADER_FRAGMENT;
551 bundle.tag = in_frag ? TAG_TEXTURE_4 : TAG_TEXTURE_4_VTX;
552 break;
553 }
554
555 default:
556 unreachable("Unknown tag");
557 break;
558 }
559
560 /* Copy the instructions into the bundle */
561 bundle.instruction_count = instructions_emitted + 1 + packed_idx;
562
563 midgard_instruction *uins = ins;
564 for (; packed_idx < bundle.instruction_count; ++packed_idx) {
565 bundle.instructions[packed_idx] = uins;
566 uins = mir_next_op(uins);
567 }
568
569 *skip = instructions_emitted;
570
571 return bundle;
572 }
573
574 /* Schedule a single block by iterating its instruction to create bundles.
575 * While we go, tally about the bundle sizes to compute the block size. */
576
577 static void
578 schedule_block(compiler_context *ctx, midgard_block *block)
579 {
580 util_dynarray_init(&block->bundles, NULL);
581
582 block->quadword_count = 0;
583
584 mir_foreach_instr_in_block(block, ins) {
585 int skip;
586 midgard_bundle bundle = schedule_bundle(ctx, block, ins, &skip);
587 util_dynarray_append(&block->bundles, midgard_bundle, bundle);
588
589 if (bundle.has_blend_constant) {
590 /* TODO: Multiblock? */
591 int quadwords_within_block = block->quadword_count + quadword_size(bundle.tag) - 1;
592 ctx->blend_constant_offset = quadwords_within_block * 0x10;
593 }
594
595 while(skip--)
596 ins = mir_next_op(ins);
597
598 block->quadword_count += quadword_size(bundle.tag);
599 }
600
601 block->is_scheduled = true;
602 }
603
604 /* The following passes reorder MIR instructions to enable better scheduling */
605
606 static void
607 midgard_pair_load_store(compiler_context *ctx, midgard_block *block)
608 {
609 mir_foreach_instr_in_block_safe(block, ins) {
610 if (ins->type != TAG_LOAD_STORE_4) continue;
611
612 /* We've found a load/store op. Check if next is also load/store. */
613 midgard_instruction *next_op = mir_next_op(ins);
614 if (&next_op->link != &block->instructions) {
615 if (next_op->type == TAG_LOAD_STORE_4) {
616 /* If so, we're done since we're a pair */
617 ins = mir_next_op(ins);
618 continue;
619 }
620
621 /* Maximum search distance to pair, to avoid register pressure disasters */
622 int search_distance = 8;
623
624 /* Otherwise, we have an orphaned load/store -- search for another load */
625 mir_foreach_instr_in_block_from(block, c, mir_next_op(ins)) {
626 /* Terminate search if necessary */
627 if (!(search_distance--)) break;
628
629 if (c->type != TAG_LOAD_STORE_4) continue;
630
631 /* We can only reorder if there are no sources */
632
633 bool deps = false;
634
635 for (unsigned s = 0; s < ARRAY_SIZE(ins->src); ++s)
636 deps |= (c->src[s] != ~0);
637
638 if (deps)
639 continue;
640
641 /* We found one! Move it up to pair and remove it from the old location */
642
643 mir_insert_instruction_before(ins, *c);
644 mir_remove_instruction(c);
645
646 break;
647 }
648 }
649 }
650 }
651
652 /* When we're 'squeezing down' the values in the IR, we maintain a hash
653 * as such */
654
655 static unsigned
656 find_or_allocate_temp(compiler_context *ctx, unsigned hash)
657 {
658 if (hash >= SSA_FIXED_MINIMUM)
659 return hash;
660
661 unsigned temp = (uintptr_t) _mesa_hash_table_u64_search(
662 ctx->hash_to_temp, hash + 1);
663
664 if (temp)
665 return temp - 1;
666
667 /* If no temp is find, allocate one */
668 temp = ctx->temp_count++;
669 ctx->max_hash = MAX2(ctx->max_hash, hash);
670
671 _mesa_hash_table_u64_insert(ctx->hash_to_temp,
672 hash + 1, (void *) ((uintptr_t) temp + 1));
673
674 return temp;
675 }
676
677 /* Reassigns numbering to get rid of gaps in the indices */
678
679 static void
680 mir_squeeze_index(compiler_context *ctx)
681 {
682 /* Reset */
683 ctx->temp_count = 0;
684 /* TODO don't leak old hash_to_temp */
685 ctx->hash_to_temp = _mesa_hash_table_u64_create(NULL);
686
687 mir_foreach_instr_global(ctx, ins) {
688 ins->dest = find_or_allocate_temp(ctx, ins->dest);
689
690 for (unsigned i = 0; i < ARRAY_SIZE(ins->src); ++i)
691 ins->src[i] = find_or_allocate_temp(ctx, ins->src[i]);
692 }
693 }
694
695 static midgard_instruction
696 v_load_store_scratch(
697 unsigned srcdest,
698 unsigned index,
699 bool is_store,
700 unsigned mask)
701 {
702 /* We index by 32-bit vec4s */
703 unsigned byte = (index * 4 * 4);
704
705 midgard_instruction ins = {
706 .type = TAG_LOAD_STORE_4,
707 .mask = mask,
708 .dest = ~0,
709 .src = { ~0, ~0, ~0 },
710 .load_store = {
711 .op = is_store ? midgard_op_st_int4 : midgard_op_ld_int4,
712 .swizzle = SWIZZLE_XYZW,
713
714 /* For register spilling - to thread local storage */
715 .arg_1 = 0xEA,
716 .arg_2 = 0x1E,
717
718 /* Splattered across, TODO combine logically */
719 .varying_parameters = (byte & 0x1FF) << 1,
720 .address = (byte >> 9)
721 },
722
723 /* If we spill an unspill, RA goes into an infinite loop */
724 .no_spill = true
725 };
726
727 if (is_store) {
728 /* r0 = r26, r1 = r27 */
729 assert(srcdest == SSA_FIXED_REGISTER(26) || srcdest == SSA_FIXED_REGISTER(27));
730 ins.src[0] = srcdest;
731 } else {
732 ins.dest = srcdest;
733 }
734
735 return ins;
736 }
737
738 /* If register allocation fails, find the best spill node and spill it to fix
739 * whatever the issue was. This spill node could be a work register (spilling
740 * to thread local storage), but it could also simply be a special register
741 * that needs to spill to become a work register. */
742
743 static void mir_spill_register(
744 compiler_context *ctx,
745 struct ra_graph *g,
746 unsigned *spill_count)
747 {
748 unsigned spill_index = ctx->temp_count;
749
750 /* Our first step is to calculate spill cost to figure out the best
751 * spill node. All nodes are equal in spill cost, but we can't spill
752 * nodes written to from an unspill */
753
754 for (unsigned i = 0; i < ctx->temp_count; ++i) {
755 ra_set_node_spill_cost(g, i, 1.0);
756 }
757
758 mir_foreach_instr_global(ctx, ins) {
759 if (ins->no_spill &&
760 ins->dest >= 0 &&
761 ins->dest < ctx->temp_count)
762 ra_set_node_spill_cost(g, ins->dest, -1.0);
763 }
764
765 int spill_node = ra_get_best_spill_node(g);
766
767 if (spill_node < 0) {
768 mir_print_shader(ctx);
769 assert(0);
770 }
771
772 /* We have a spill node, so check the class. Work registers
773 * legitimately spill to TLS, but special registers just spill to work
774 * registers */
775
776 unsigned class = ra_get_node_class(g, spill_node);
777 bool is_special = (class >> 2) != REG_CLASS_WORK;
778 bool is_special_w = (class >> 2) == REG_CLASS_TEXW;
779
780 /* Allocate TLS slot (maybe) */
781 unsigned spill_slot = !is_special ? (*spill_count)++ : 0;
782
783 /* For TLS, replace all stores to the spilled node. For
784 * special reads, just keep as-is; the class will be demoted
785 * implicitly. For special writes, spill to a work register */
786
787 if (!is_special || is_special_w) {
788 if (is_special_w)
789 spill_slot = spill_index++;
790
791 mir_foreach_instr_global_safe(ctx, ins) {
792 if (ins->dest != spill_node) continue;
793
794 midgard_instruction st;
795
796 if (is_special_w) {
797 st = v_mov(spill_node, blank_alu_src, spill_slot);
798 st.no_spill = true;
799 } else {
800 ins->dest = SSA_FIXED_REGISTER(26);
801 st = v_load_store_scratch(ins->dest, spill_slot, true, ins->mask);
802 }
803
804 /* Hint: don't rewrite this node */
805 st.hint = true;
806
807 mir_insert_instruction_before(mir_next_op(ins), st);
808
809 if (!is_special)
810 ctx->spills++;
811 }
812 }
813
814 /* For special reads, figure out how many components we need */
815 unsigned read_mask = 0;
816
817 mir_foreach_instr_global_safe(ctx, ins) {
818 read_mask |= mir_mask_of_read_components(ins, spill_node);
819 }
820
821 /* Insert a load from TLS before the first consecutive
822 * use of the node, rewriting to use spilled indices to
823 * break up the live range. Or, for special, insert a
824 * move. Ironically the latter *increases* register
825 * pressure, but the two uses of the spilling mechanism
826 * are somewhat orthogonal. (special spilling is to use
827 * work registers to back special registers; TLS
828 * spilling is to use memory to back work registers) */
829
830 mir_foreach_block(ctx, block) {
831 bool consecutive_skip = false;
832 unsigned consecutive_index = 0;
833
834 mir_foreach_instr_in_block(block, ins) {
835 /* We can't rewrite the moves used to spill in the
836 * first place. These moves are hinted. */
837 if (ins->hint) continue;
838
839 if (!mir_has_arg(ins, spill_node)) {
840 consecutive_skip = false;
841 continue;
842 }
843
844 if (consecutive_skip) {
845 /* Rewrite */
846 mir_rewrite_index_src_single(ins, spill_node, consecutive_index);
847 continue;
848 }
849
850 if (!is_special_w) {
851 consecutive_index = ++spill_index;
852
853 midgard_instruction *before = ins;
854
855 /* For a csel, go back one more not to break up the bundle */
856 if (ins->type == TAG_ALU_4 && OP_IS_CSEL(ins->alu.op))
857 before = mir_prev_op(before);
858
859 midgard_instruction st;
860
861 if (is_special) {
862 /* Move */
863 st = v_mov(spill_node, blank_alu_src, consecutive_index);
864 st.no_spill = true;
865 } else {
866 /* TLS load */
867 st = v_load_store_scratch(consecutive_index, spill_slot, false, 0xF);
868 }
869
870 /* Mask the load based on the component count
871 * actually needed to prvent RA loops */
872
873 st.mask = read_mask;
874
875 mir_insert_instruction_before(before, st);
876 // consecutive_skip = true;
877 } else {
878 /* Special writes already have their move spilled in */
879 consecutive_index = spill_slot;
880 }
881
882
883 /* Rewrite to use */
884 mir_rewrite_index_src_single(ins, spill_node, consecutive_index);
885
886 if (!is_special)
887 ctx->fills++;
888 }
889 }
890
891 /* Reset hints */
892
893 mir_foreach_instr_global(ctx, ins) {
894 ins->hint = false;
895 }
896 }
897
898 void
899 schedule_program(compiler_context *ctx)
900 {
901 struct ra_graph *g = NULL;
902 bool spilled = false;
903 int iter_count = 1000; /* max iterations */
904
905 /* Number of 128-bit slots in memory we've spilled into */
906 unsigned spill_count = 0;
907
908 midgard_promote_uniforms(ctx, 16);
909
910 mir_foreach_block(ctx, block) {
911 midgard_pair_load_store(ctx, block);
912 }
913
914 /* Must be lowered right before RA */
915 mir_squeeze_index(ctx);
916 mir_lower_special_reads(ctx);
917
918 /* Lowering can introduce some dead moves */
919
920 mir_foreach_block(ctx, block) {
921 midgard_opt_dead_move_eliminate(ctx, block);
922 }
923
924 do {
925 if (spilled)
926 mir_spill_register(ctx, g, &spill_count);
927
928 mir_squeeze_index(ctx);
929
930 g = NULL;
931 g = allocate_registers(ctx, &spilled);
932 } while(spilled && ((iter_count--) > 0));
933
934 /* We can simplify a bit after RA */
935
936 mir_foreach_block(ctx, block) {
937 midgard_opt_post_move_eliminate(ctx, block, g);
938 }
939
940 /* After RA finishes, we schedule all at once */
941
942 mir_foreach_block(ctx, block) {
943 schedule_block(ctx, block);
944 }
945
946 /* Finally, we create pipeline registers as a peephole pass after
947 * scheduling. This isn't totally optimal, since there are cases where
948 * the usage of pipeline registers can eliminate spills, but it does
949 * save some power */
950
951 mir_create_pipeline_registers(ctx);
952
953 if (iter_count <= 0) {
954 fprintf(stderr, "panfrost: Gave up allocating registers, rendering will be incomplete\n");
955 assert(0);
956 }
957
958 /* Report spilling information. spill_count is in 128-bit slots (vec4 x
959 * fp32), but tls_size is in bytes, so multiply by 16 */
960
961 ctx->tls_size = spill_count * 16;
962
963 install_registers(ctx, g);
964 }