2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 #include "midgard_ops.h"
26 #include "midgard_quirks.h"
27 #include "util/u_memory.h"
29 /* Scheduling for Midgard is complicated, to say the least. ALU instructions
30 * must be grouped into VLIW bundles according to following model:
33 * [VADD] [SMUL] [VLUT]
35 * A given instruction can execute on some subset of the units (or a few can
36 * execute on all). Instructions can be either vector or scalar; only scalar
37 * instructions can execute on SADD/SMUL units. Units on a given line execute
38 * in parallel. Subsequent lines execute separately and can pass results
39 * directly via pipeline registers r24/r25, bypassing the register file.
41 * A bundle can optionally have 128-bits of embedded constants, shared across
42 * all of the instructions within a bundle.
44 * Instructions consuming conditionals (branches and conditional selects)
45 * require their condition to be written into the conditional register (r31)
46 * within the same bundle they are consumed.
48 * Fragment writeout requires its argument to be written in full within the
49 * same bundle as the branch, with no hanging dependencies.
51 * Load/store instructions are also in bundles of simply two instructions, and
52 * texture instructions have no bundling.
54 * -------------------------------------------------------------------------
58 /* We create the dependency graph with per-byte granularity */
63 add_dependency(struct util_dynarray
*table
, unsigned index
, uint16_t mask
, midgard_instruction
**instructions
, unsigned child
)
65 for (unsigned i
= 0; i
< BYTE_COUNT
; ++i
) {
66 if (!(mask
& (1 << i
)))
69 struct util_dynarray
*parents
= &table
[(BYTE_COUNT
* index
) + i
];
71 util_dynarray_foreach(parents
, unsigned, parent
) {
72 BITSET_WORD
*dependents
= instructions
[*parent
]->dependents
;
74 /* Already have the dependency */
75 if (BITSET_TEST(dependents
, child
))
78 BITSET_SET(dependents
, child
);
79 instructions
[child
]->nr_dependencies
++;
85 mark_access(struct util_dynarray
*table
, unsigned index
, uint16_t mask
, unsigned parent
)
87 for (unsigned i
= 0; i
< BYTE_COUNT
; ++i
) {
88 if (!(mask
& (1 << i
)))
91 util_dynarray_append(&table
[(BYTE_COUNT
* index
) + i
], unsigned, parent
);
96 mir_create_dependency_graph(midgard_instruction
**instructions
, unsigned count
, unsigned node_count
)
98 size_t sz
= node_count
* BYTE_COUNT
;
100 struct util_dynarray
*last_read
= calloc(sizeof(struct util_dynarray
), sz
);
101 struct util_dynarray
*last_write
= calloc(sizeof(struct util_dynarray
), sz
);
103 for (unsigned i
= 0; i
< sz
; ++i
) {
104 util_dynarray_init(&last_read
[i
], NULL
);
105 util_dynarray_init(&last_write
[i
], NULL
);
108 /* Initialize dependency graph */
109 for (unsigned i
= 0; i
< count
; ++i
) {
110 instructions
[i
]->dependents
=
111 calloc(BITSET_WORDS(count
), sizeof(BITSET_WORD
));
113 instructions
[i
]->nr_dependencies
= 0;
116 /* Populate dependency graph */
117 for (signed i
= count
- 1; i
>= 0; --i
) {
118 if (instructions
[i
]->compact_branch
)
121 unsigned dest
= instructions
[i
]->dest
;
122 unsigned mask
= mir_bytemask(instructions
[i
]);
124 mir_foreach_src((*instructions
), s
) {
125 unsigned src
= instructions
[i
]->src
[s
];
127 if (src
< node_count
) {
128 unsigned readmask
= mir_bytemask_of_read_components(instructions
[i
], src
);
129 add_dependency(last_write
, src
, readmask
, instructions
, i
);
133 if (dest
< node_count
) {
134 add_dependency(last_read
, dest
, mask
, instructions
, i
);
135 add_dependency(last_write
, dest
, mask
, instructions
, i
);
136 mark_access(last_write
, dest
, mask
, i
);
139 mir_foreach_src((*instructions
), s
) {
140 unsigned src
= instructions
[i
]->src
[s
];
142 if (src
< node_count
) {
143 unsigned readmask
= mir_bytemask_of_read_components(instructions
[i
], src
);
144 mark_access(last_read
, src
, readmask
, i
);
149 /* If there is a branch, all instructions depend on it, as interblock
150 * execution must be purely in-order */
152 if (instructions
[count
- 1]->compact_branch
) {
153 BITSET_WORD
*dependents
= instructions
[count
- 1]->dependents
;
155 for (signed i
= count
- 2; i
>= 0; --i
) {
156 if (BITSET_TEST(dependents
, i
))
159 BITSET_SET(dependents
, i
);
160 instructions
[i
]->nr_dependencies
++;
164 /* Free the intermediate structures */
165 for (unsigned i
= 0; i
< sz
; ++i
) {
166 util_dynarray_fini(&last_read
[i
]);
167 util_dynarray_fini(&last_write
[i
]);
174 /* Does the mask cover more than a scalar? */
177 is_single_component_mask(unsigned mask
)
181 for (int c
= 0; c
< 8; ++c
) {
186 return components
== 1;
189 /* Helpers for scheudling */
192 mir_is_scalar(midgard_instruction
*ains
)
194 /* Do we try to use it as a vector op? */
195 if (!is_single_component_mask(ains
->mask
))
198 /* Otherwise, check mode hazards */
199 bool could_scalar
= true;
201 /* Only 16/32-bit can run on a scalar unit */
202 could_scalar
&= ains
->alu
.reg_mode
!= midgard_reg_mode_8
;
203 could_scalar
&= ains
->alu
.reg_mode
!= midgard_reg_mode_64
;
204 could_scalar
&= ains
->alu
.dest_override
== midgard_dest_override_none
;
206 if (ains
->alu
.reg_mode
== midgard_reg_mode_16
) {
207 /* If we're running in 16-bit mode, we
208 * can't have any 8-bit sources on the
209 * scalar unit (since the scalar unit
210 * doesn't understand 8-bit) */
212 midgard_vector_alu_src s1
=
213 vector_alu_from_unsigned(ains
->alu
.src1
);
215 could_scalar
&= !s1
.half
;
217 midgard_vector_alu_src s2
=
218 vector_alu_from_unsigned(ains
->alu
.src2
);
220 could_scalar
&= !s2
.half
;
226 /* How many bytes does this ALU instruction add to the bundle? */
229 bytes_for_instruction(midgard_instruction
*ains
)
231 if (ains
->unit
& UNITS_ANY_VECTOR
)
232 return sizeof(midgard_reg_info
) + sizeof(midgard_vector_alu
);
233 else if (ains
->unit
== ALU_ENAB_BRANCH
)
234 return sizeof(midgard_branch_extended
);
235 else if (ains
->compact_branch
)
236 return sizeof(ains
->br_compact
);
238 return sizeof(midgard_reg_info
) + sizeof(midgard_scalar_alu
);
241 /* We would like to flatten the linked list of midgard_instructions in a bundle
242 * to an array of pointers on the heap for easy indexing */
244 static midgard_instruction
**
245 flatten_mir(midgard_block
*block
, unsigned *len
)
247 *len
= list_length(&block
->instructions
);
252 midgard_instruction
**instructions
=
253 calloc(sizeof(midgard_instruction
*), *len
);
257 mir_foreach_instr_in_block(block
, ins
)
258 instructions
[i
++] = ins
;
263 /* The worklist is the set of instructions that can be scheduled now; that is,
264 * the set of instructions with no remaining dependencies */
267 mir_initialize_worklist(BITSET_WORD
*worklist
, midgard_instruction
**instructions
, unsigned count
)
269 for (unsigned i
= 0; i
< count
; ++i
) {
270 if (instructions
[i
]->nr_dependencies
== 0)
271 BITSET_SET(worklist
, i
);
275 /* Update the worklist after an instruction terminates. Remove its edges from
276 * the graph and if that causes any node to have no dependencies, add it to the
281 BITSET_WORD
*worklist
, unsigned count
,
282 midgard_instruction
**instructions
, midgard_instruction
*done
)
284 /* Sanity check: if no instruction terminated, there is nothing to do.
285 * If the instruction that terminated had dependencies, that makes no
286 * sense and means we messed up the worklist. Finally, as the purpose
287 * of this routine is to update dependents, we abort early if there are
288 * no dependents defined. */
293 assert(done
->nr_dependencies
== 0);
295 if (!done
->dependents
)
298 /* We have an instruction with dependents. Iterate each dependent to
299 * remove one dependency (`done`), adding dependents to the worklist
303 BITSET_FOREACH_SET(i
, done
->dependents
, count
) {
304 assert(instructions
[i
]->nr_dependencies
);
306 if (!(--instructions
[i
]->nr_dependencies
))
307 BITSET_SET(worklist
, i
);
310 free(done
->dependents
);
313 /* While scheduling, we need to choose instructions satisfying certain
314 * criteria. As we schedule backwards, we choose the *last* instruction in the
315 * worklist to simulate in-order scheduling. Chosen instructions must satisfy a
316 * given predicate. */
318 struct midgard_predicate
{
319 /* TAG or ~0 for dont-care */
322 /* True if we want to pop off the chosen instruction */
325 /* For ALU, choose only this unit */
328 /* State for bundle constants. constants is the actual constants
329 * for the bundle. constant_count is the number of bytes (up to
330 * 16) currently in use for constants. When picking in destructive
331 * mode, the constants array will be updated, and the instruction
332 * will be adjusted to index into the constants array */
334 midgard_constants
*constants
;
335 unsigned constant_mask
;
338 /* Exclude this destination (if not ~0) */
341 /* Don't schedule instructions consuming conditionals (since we already
342 * scheduled one). Excludes conditional branches and csel */
345 /* Require a minimal mask and (if nonzero) given destination. Used for
346 * writeout optimizations */
352 /* For an instruction that can fit, adjust it to fit and update the constants
353 * array, in destructive mode. Returns whether the fitting was successful. */
356 mir_adjust_constants(midgard_instruction
*ins
,
357 struct midgard_predicate
*pred
,
360 /* Blend constants dominate */
361 if (ins
->has_blend_constant
) {
362 if (pred
->constant_mask
)
364 else if (destructive
) {
365 pred
->blend_constant
= true;
366 pred
->constant_mask
= 0xffff;
371 /* No constant, nothing to adjust */
372 if (!ins
->has_constants
)
375 unsigned r_constant
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
376 midgard_reg_mode dst_mode
= mir_typesize(ins
);
378 unsigned bundle_constant_mask
= pred
->constant_mask
;
379 unsigned comp_mapping
[2][16] = { };
380 uint8_t bundle_constants
[16];
382 memcpy(bundle_constants
, pred
->constants
, 16);
384 /* Let's try to find a place for each active component of the constant
387 for (unsigned src
= 0; src
< 2; ++src
) {
388 if (ins
->src
[src
] != SSA_FIXED_REGISTER(REGISTER_CONSTANT
))
391 midgard_reg_mode src_mode
= mir_srcsize(ins
, src
);
392 unsigned type_size
= mir_bytes_for_mode(src_mode
);
393 unsigned max_comp
= 16 / type_size
;
394 unsigned comp_mask
= mir_from_bytemask(mir_bytemask_of_read_components_index(ins
, src
),
396 unsigned type_mask
= (1 << type_size
) - 1;
398 for (unsigned comp
= 0; comp
< max_comp
; comp
++) {
399 if (!(comp_mask
& (1 << comp
)))
402 uint8_t *constantp
= ins
->constants
.u8
+ (type_size
* comp
);
403 unsigned best_reuse_bytes
= 0;
404 signed best_place
= -1;
407 for (i
= 0; i
< 16; i
+= type_size
) {
408 unsigned reuse_bytes
= 0;
410 for (j
= 0; j
< type_size
; j
++) {
411 if (!(bundle_constant_mask
& (1 << (i
+ j
))))
413 if (constantp
[j
] != bundle_constants
[i
+ j
])
419 /* Select the place where existing bytes can be
420 * reused so we leave empty slots to others
422 if (j
== type_size
&&
423 (reuse_bytes
> best_reuse_bytes
|| best_place
< 0)) {
424 best_reuse_bytes
= reuse_bytes
;
430 /* This component couldn't fit in the remaining constant slot,
431 * no need check the remaining components, bail out now
436 memcpy(&bundle_constants
[i
], constantp
, type_size
);
437 bundle_constant_mask
|= type_mask
<< best_place
;
438 comp_mapping
[src
][comp
] = best_place
/ type_size
;
442 /* If non-destructive, we're done */
446 /* Otherwise update the constant_mask and constant values */
447 pred
->constant_mask
= bundle_constant_mask
;
448 memcpy(pred
->constants
, bundle_constants
, 16);
450 /* Use comp_mapping as a swizzle */
451 mir_foreach_src(ins
, s
) {
452 if (ins
->src
[s
] == r_constant
)
453 mir_compose_swizzle(ins
->swizzle
[s
], comp_mapping
[s
], ins
->swizzle
[s
]);
459 static midgard_instruction
*
460 mir_choose_instruction(
461 midgard_instruction
**instructions
,
462 BITSET_WORD
*worklist
, unsigned count
,
463 struct midgard_predicate
*predicate
)
465 /* Parse the predicate */
466 unsigned tag
= predicate
->tag
;
467 bool alu
= tag
== TAG_ALU_4
;
468 unsigned unit
= predicate
->unit
;
469 bool branch
= alu
&& (unit
== ALU_ENAB_BR_COMPACT
);
470 bool scalar
= (unit
!= ~0) && (unit
& UNITS_SCALAR
);
471 bool no_cond
= predicate
->no_cond
;
473 unsigned mask
= predicate
->mask
;
474 unsigned dest
= predicate
->dest
;
475 bool needs_dest
= mask
& 0xF;
477 /* Iterate to find the best instruction satisfying the predicate */
480 signed best_index
= -1;
481 bool best_conditional
= false;
483 /* Enforce a simple metric limiting distance to keep down register
484 * pressure. TOOD: replace with liveness tracking for much better
487 unsigned max_active
= 0;
488 unsigned max_distance
= 6;
490 BITSET_FOREACH_SET(i
, worklist
, count
) {
491 max_active
= MAX2(max_active
, i
);
494 BITSET_FOREACH_SET(i
, worklist
, count
) {
495 if ((max_active
- i
) >= max_distance
)
498 if (tag
!= ~0 && instructions
[i
]->type
!= tag
)
501 if (predicate
->exclude
!= ~0 && instructions
[i
]->dest
== predicate
->exclude
)
504 if (alu
&& !branch
&& !(alu_opcode_props
[instructions
[i
]->alu
.op
].props
& unit
))
507 if (branch
&& !instructions
[i
]->compact_branch
)
510 if (alu
&& scalar
&& !mir_is_scalar(instructions
[i
]))
513 if (alu
&& !mir_adjust_constants(instructions
[i
], predicate
, false))
516 if (needs_dest
&& instructions
[i
]->dest
!= dest
)
519 if (mask
&& ((~instructions
[i
]->mask
) & mask
))
522 bool conditional
= alu
&& !branch
&& OP_IS_CSEL(instructions
[i
]->alu
.op
);
523 conditional
|= (branch
&& instructions
[i
]->branch
.conditional
);
525 if (conditional
&& no_cond
)
528 /* Simulate in-order scheduling */
529 if ((signed) i
< best_index
)
533 best_conditional
= conditional
;
537 /* Did we find anything? */
542 /* If we found something, remove it from the worklist */
543 assert(best_index
< count
);
545 if (predicate
->destructive
) {
546 BITSET_CLEAR(worklist
, best_index
);
549 mir_adjust_constants(instructions
[best_index
], predicate
, true);
551 /* Once we schedule a conditional, we can't again */
552 predicate
->no_cond
|= best_conditional
;
555 return instructions
[best_index
];
558 /* Still, we don't choose instructions in a vacuum. We need a way to choose the
559 * best bundle type (ALU, load/store, texture). Nondestructive. */
563 midgard_instruction
**instructions
,
564 BITSET_WORD
*worklist
, unsigned count
)
566 /* At the moment, our algorithm is very simple - use the bundle of the
567 * best instruction, regardless of what else could be scheduled
568 * alongside it. This is not optimal but it works okay for in-order */
570 struct midgard_predicate predicate
= {
572 .destructive
= false,
576 midgard_instruction
*chosen
= mir_choose_instruction(instructions
, worklist
, count
, &predicate
);
584 /* We want to choose an ALU instruction filling a given unit */
586 mir_choose_alu(midgard_instruction
**slot
,
587 midgard_instruction
**instructions
,
588 BITSET_WORD
*worklist
, unsigned len
,
589 struct midgard_predicate
*predicate
,
592 /* Did we already schedule to this slot? */
596 /* Try to schedule something, if not */
597 predicate
->unit
= unit
;
598 *slot
= mir_choose_instruction(instructions
, worklist
, len
, predicate
);
600 /* Store unit upon scheduling */
601 if (*slot
&& !((*slot
)->compact_branch
))
602 (*slot
)->unit
= unit
;
605 /* When we are scheduling a branch/csel, we need the consumed condition in the
606 * same block as a pipeline register. There are two options to enable this:
608 * - Move the conditional into the bundle. Preferred, but only works if the
609 * conditional is used only once and is from this block.
610 * - Copy the conditional.
612 * We search for the conditional. If it's in this block, single-use, and
613 * without embedded constants, we schedule it immediately. Otherwise, we
614 * schedule a move for it.
616 * mir_comparison_mobile is a helper to find the moveable condition.
620 mir_comparison_mobile(
621 compiler_context
*ctx
,
622 midgard_instruction
**instructions
,
623 struct midgard_predicate
*predicate
,
627 if (!mir_single_use(ctx
, cond
))
632 for (unsigned i
= 0; i
< count
; ++i
) {
633 if (instructions
[i
]->dest
!= cond
)
636 /* Must fit in an ALU bundle */
637 if (instructions
[i
]->type
!= TAG_ALU_4
)
640 /* If it would itself require a condition, that's recursive */
641 if (OP_IS_CSEL(instructions
[i
]->alu
.op
))
644 /* We'll need to rewrite to .w but that doesn't work for vector
645 * ops that don't replicate (ball/bany), so bail there */
647 if (GET_CHANNEL_COUNT(alu_opcode_props
[instructions
[i
]->alu
.op
].props
))
650 /* Ensure it will fit with constants */
652 if (!mir_adjust_constants(instructions
[i
], predicate
, false))
655 /* Ensure it is written only once */
663 /* Inject constants now that we are sure we want to */
665 mir_adjust_constants(instructions
[ret
], predicate
, true);
670 /* Using the information about the moveable conditional itself, we either pop
671 * that condition off the worklist for use now, or create a move to
672 * artificially schedule instead as a fallback */
674 static midgard_instruction
*
675 mir_schedule_comparison(
676 compiler_context
*ctx
,
677 midgard_instruction
**instructions
,
678 struct midgard_predicate
*predicate
,
679 BITSET_WORD
*worklist
, unsigned count
,
680 unsigned cond
, bool vector
, unsigned *swizzle
,
681 midgard_instruction
*user
)
683 /* TODO: swizzle when scheduling */
685 (!vector
&& (swizzle
[0] == 0)) ?
686 mir_comparison_mobile(ctx
, instructions
, predicate
, count
, cond
) : ~0;
688 /* If we can, schedule the condition immediately */
689 if ((comp_i
!= ~0) && BITSET_TEST(worklist
, comp_i
)) {
690 assert(comp_i
< count
);
691 BITSET_CLEAR(worklist
, comp_i
);
692 return instructions
[comp_i
];
695 /* Otherwise, we insert a move */
697 midgard_instruction mov
= v_mov(cond
, cond
);
698 mov
.mask
= vector
? 0xF : 0x1;
699 memcpy(mov
.swizzle
[1], swizzle
, sizeof(mov
.swizzle
[1]));
701 return mir_insert_instruction_before(ctx
, user
, mov
);
704 /* Most generally, we need instructions writing to r31 in the appropriate
707 static midgard_instruction
*
708 mir_schedule_condition(compiler_context
*ctx
,
709 struct midgard_predicate
*predicate
,
710 BITSET_WORD
*worklist
, unsigned count
,
711 midgard_instruction
**instructions
,
712 midgard_instruction
*last
)
714 /* For a branch, the condition is the only argument; for csel, third */
715 bool branch
= last
->compact_branch
;
716 unsigned condition_index
= branch
? 0 : 2;
718 /* csel_v is vector; otherwise, conditions are scalar */
719 bool vector
= !branch
&& OP_IS_CSEL_V(last
->alu
.op
);
721 /* Grab the conditional instruction */
723 midgard_instruction
*cond
= mir_schedule_comparison(
724 ctx
, instructions
, predicate
, worklist
, count
, last
->src
[condition_index
],
725 vector
, last
->swizzle
[2], last
);
727 /* We have exclusive reign over this (possibly move) conditional
728 * instruction. We can rewrite into a pipeline conditional register */
730 predicate
->exclude
= cond
->dest
;
731 cond
->dest
= SSA_FIXED_REGISTER(31);
734 cond
->mask
= (1 << COMPONENT_W
);
736 mir_foreach_src(cond
, s
) {
737 if (cond
->src
[s
] == ~0)
740 for (unsigned q
= 0; q
< 4; ++q
)
741 cond
->swizzle
[s
][q
+ COMPONENT_W
] = cond
->swizzle
[s
][q
];
745 /* Schedule the unit: csel is always in the latter pipeline, so a csel
746 * condition must be in the former pipeline stage (vmul/sadd),
747 * depending on scalar/vector of the instruction itself. A branch must
748 * be written from the latter pipeline stage and a branch condition is
749 * always scalar, so it is always in smul (exception: ball/bany, which
753 cond
->unit
= UNIT_SMUL
;
755 cond
->unit
= vector
? UNIT_VMUL
: UNIT_SADD
;
760 /* Schedules a single bundle of the given type */
762 static midgard_bundle
763 mir_schedule_texture(
764 midgard_instruction
**instructions
,
765 BITSET_WORD
*worklist
, unsigned len
)
767 struct midgard_predicate predicate
= {
768 .tag
= TAG_TEXTURE_4
,
773 midgard_instruction
*ins
=
774 mir_choose_instruction(instructions
, worklist
, len
, &predicate
);
776 mir_update_worklist(worklist
, len
, instructions
, ins
);
778 struct midgard_bundle out
= {
779 .tag
= TAG_TEXTURE_4
,
780 .instruction_count
= 1,
781 .instructions
= { ins
}
787 static midgard_bundle
789 midgard_instruction
**instructions
,
790 BITSET_WORD
*worklist
, unsigned len
)
792 struct midgard_predicate predicate
= {
793 .tag
= TAG_LOAD_STORE_4
,
798 /* Try to pick two load/store ops. Second not gauranteed to exist */
800 midgard_instruction
*ins
=
801 mir_choose_instruction(instructions
, worklist
, len
, &predicate
);
803 midgard_instruction
*pair
=
804 mir_choose_instruction(instructions
, worklist
, len
, &predicate
);
806 struct midgard_bundle out
= {
807 .tag
= TAG_LOAD_STORE_4
,
808 .instruction_count
= pair
? 2 : 1,
809 .instructions
= { ins
, pair
}
812 /* We have to update the worklist atomically, since the two
813 * instructions run concurrently (TODO: verify it's not pipelined) */
815 mir_update_worklist(worklist
, len
, instructions
, ins
);
816 mir_update_worklist(worklist
, len
, instructions
, pair
);
821 static midgard_bundle
823 compiler_context
*ctx
,
824 midgard_instruction
**instructions
,
825 BITSET_WORD
*worklist
, unsigned len
)
827 struct midgard_bundle bundle
= {};
829 unsigned bytes_emitted
= sizeof(bundle
.control
);
831 struct midgard_predicate predicate
= {
835 .constants
= &bundle
.constants
838 midgard_instruction
*vmul
= NULL
;
839 midgard_instruction
*vadd
= NULL
;
840 midgard_instruction
*vlut
= NULL
;
841 midgard_instruction
*smul
= NULL
;
842 midgard_instruction
*sadd
= NULL
;
843 midgard_instruction
*branch
= NULL
;
845 mir_choose_alu(&branch
, instructions
, worklist
, len
, &predicate
, ALU_ENAB_BR_COMPACT
);
846 mir_update_worklist(worklist
, len
, instructions
, branch
);
847 bool writeout
= branch
&& branch
->writeout
;
849 if (branch
&& branch
->branch
.conditional
) {
850 midgard_instruction
*cond
= mir_schedule_condition(ctx
, &predicate
, worklist
, len
, instructions
, branch
);
852 if (cond
->unit
== UNIT_VADD
)
854 else if (cond
->unit
== UNIT_SMUL
)
857 unreachable("Bad condition");
860 mir_choose_alu(&smul
, instructions
, worklist
, len
, &predicate
, UNIT_SMUL
);
863 mir_choose_alu(&vlut
, instructions
, worklist
, len
, &predicate
, UNIT_VLUT
);
867 bundle
.last_writeout
= branch
->last_writeout
;
869 vadd
= ralloc(ctx
, midgard_instruction
);
870 *vadd
= v_mov(~0, make_compiler_temp(ctx
));
872 if (!ctx
->is_blend
) {
873 vadd
->alu
.op
= midgard_alu_op_iadd
;
874 vadd
->src
[0] = SSA_FIXED_REGISTER(31);
876 for (unsigned c
= 0; c
< 16; ++c
)
877 vadd
->swizzle
[0][c
] = COMPONENT_X
;
879 vadd
->has_inline_constant
= true;
880 vadd
->inline_constant
= 0;
882 vadd
->src
[1] = SSA_FIXED_REGISTER(1);
884 for (unsigned c
= 0; c
< 16; ++c
)
885 vadd
->swizzle
[1][c
] = COMPONENT_W
;
888 vadd
->unit
= UNIT_VADD
;
890 branch
->src
[2] = vadd
->dest
;
893 mir_choose_alu(&vadd
, instructions
, worklist
, len
, &predicate
, UNIT_VADD
);
895 mir_update_worklist(worklist
, len
, instructions
, vlut
);
896 mir_update_worklist(worklist
, len
, instructions
, vadd
);
897 mir_update_worklist(worklist
, len
, instructions
, smul
);
899 bool vadd_csel
= vadd
&& OP_IS_CSEL(vadd
->alu
.op
);
900 bool smul_csel
= smul
&& OP_IS_CSEL(smul
->alu
.op
);
902 if (vadd_csel
|| smul_csel
) {
903 midgard_instruction
*ins
= vadd_csel
? vadd
: smul
;
904 midgard_instruction
*cond
= mir_schedule_condition(ctx
, &predicate
, worklist
, len
, instructions
, ins
);
906 if (cond
->unit
== UNIT_VMUL
)
908 else if (cond
->unit
== UNIT_SADD
)
911 unreachable("Bad condition");
914 /* If we have a render target reference, schedule a move for it */
916 if (writeout
&& (branch
->constants
.u32
[0] || ctx
->is_blend
)) {
917 sadd
= ralloc(ctx
, midgard_instruction
);
918 *sadd
= v_mov(~0, make_compiler_temp(ctx
));
919 sadd
->unit
= UNIT_SADD
;
921 sadd
->has_inline_constant
= true;
922 sadd
->inline_constant
= branch
->constants
.u32
[0];
923 branch
->src
[1] = sadd
->dest
;
926 /* Stage 2, let's schedule sadd before vmul for writeout */
927 mir_choose_alu(&sadd
, instructions
, worklist
, len
, &predicate
, UNIT_SADD
);
929 /* Check if writeout reads its own register */
931 if (branch
&& branch
->writeout
) {
932 midgard_instruction
*stages
[] = { sadd
, vadd
, smul
};
933 unsigned src
= (branch
->src
[0] == ~0) ? SSA_FIXED_REGISTER(0) : branch
->src
[0];
934 unsigned writeout_mask
= 0x0;
935 bool bad_writeout
= false;
937 for (unsigned i
= 0; i
< ARRAY_SIZE(stages
); ++i
) {
941 if (stages
[i
]->dest
!= src
)
944 writeout_mask
|= stages
[i
]->mask
;
945 bad_writeout
|= mir_has_arg(stages
[i
], branch
->src
[0]);
948 /* It's possible we'll be able to schedule something into vmul
949 * to fill r0. Let's peak into the future, trying to schedule
950 * vmul specially that way. */
952 if (!bad_writeout
&& writeout_mask
!= 0xF) {
953 predicate
.unit
= UNIT_VMUL
;
954 predicate
.dest
= src
;
955 predicate
.mask
= writeout_mask
^ 0xF;
957 struct midgard_instruction
*peaked
=
958 mir_choose_instruction(instructions
, worklist
, len
, &predicate
);
962 vmul
->unit
= UNIT_VMUL
;
963 writeout_mask
|= predicate
.mask
;
964 assert(writeout_mask
== 0xF);
968 predicate
.dest
= predicate
.mask
= 0;
971 /* Finally, add a move if necessary */
972 if (bad_writeout
|| writeout_mask
!= 0xF) {
973 unsigned temp
= (branch
->src
[0] == ~0) ? SSA_FIXED_REGISTER(0) : make_compiler_temp(ctx
);
975 vmul
= ralloc(ctx
, midgard_instruction
);
976 *vmul
= v_mov(src
, temp
);
977 vmul
->unit
= UNIT_VMUL
;
978 vmul
->mask
= 0xF ^ writeout_mask
;
980 /* Rewrite to use our temp */
982 for (unsigned i
= 0; i
< ARRAY_SIZE(stages
); ++i
) {
984 mir_rewrite_index_dst_single(stages
[i
], src
, temp
);
987 mir_rewrite_index_src_single(branch
, src
, temp
);
991 mir_choose_alu(&vmul
, instructions
, worklist
, len
, &predicate
, UNIT_VMUL
);
993 mir_update_worklist(worklist
, len
, instructions
, vmul
);
994 mir_update_worklist(worklist
, len
, instructions
, sadd
);
996 bundle
.has_blend_constant
= predicate
.blend_constant
;
997 bundle
.has_embedded_constants
= predicate
.constant_mask
!= 0;
999 unsigned padding
= 0;
1001 /* Now that we have finished scheduling, build up the bundle */
1002 midgard_instruction
*stages
[] = { vmul
, sadd
, vadd
, smul
, vlut
, branch
};
1004 for (unsigned i
= 0; i
< ARRAY_SIZE(stages
); ++i
) {
1006 bundle
.control
|= stages
[i
]->unit
;
1007 bytes_emitted
+= bytes_for_instruction(stages
[i
]);
1008 bundle
.instructions
[bundle
.instruction_count
++] = stages
[i
];
1012 /* Pad ALU op to nearest word */
1014 if (bytes_emitted
& 15) {
1015 padding
= 16 - (bytes_emitted
& 15);
1016 bytes_emitted
+= padding
;
1019 /* Constants must always be quadwords */
1020 if (bundle
.has_embedded_constants
)
1021 bytes_emitted
+= 16;
1023 /* Size ALU instruction for tag */
1024 bundle
.tag
= (TAG_ALU_4
) + (bytes_emitted
/ 16) - 1;
1026 /* MRT capable GPUs use a special writeout procedure */
1027 if (writeout
&& !(ctx
->quirks
& MIDGARD_NO_UPPER_ALU
))
1030 bundle
.padding
= padding
;
1031 bundle
.control
|= bundle
.tag
;
1036 /* Schedule a single block by iterating its instruction to create bundles.
1037 * While we go, tally about the bundle sizes to compute the block size. */
1041 schedule_block(compiler_context
*ctx
, midgard_block
*block
)
1043 /* Copy list to dynamic array */
1045 midgard_instruction
**instructions
= flatten_mir(block
, &len
);
1050 /* Calculate dependencies and initial worklist */
1051 unsigned node_count
= ctx
->temp_count
+ 1;
1052 mir_create_dependency_graph(instructions
, len
, node_count
);
1054 /* Allocate the worklist */
1055 size_t sz
= BITSET_WORDS(len
) * sizeof(BITSET_WORD
);
1056 BITSET_WORD
*worklist
= calloc(sz
, 1);
1057 mir_initialize_worklist(worklist
, instructions
, len
);
1059 struct util_dynarray bundles
;
1060 util_dynarray_init(&bundles
, NULL
);
1062 block
->quadword_count
= 0;
1063 unsigned blend_offset
= 0;
1066 unsigned tag
= mir_choose_bundle(instructions
, worklist
, len
);
1067 midgard_bundle bundle
;
1069 if (tag
== TAG_TEXTURE_4
)
1070 bundle
= mir_schedule_texture(instructions
, worklist
, len
);
1071 else if (tag
== TAG_LOAD_STORE_4
)
1072 bundle
= mir_schedule_ldst(instructions
, worklist
, len
);
1073 else if (tag
== TAG_ALU_4
)
1074 bundle
= mir_schedule_alu(ctx
, instructions
, worklist
, len
);
1078 util_dynarray_append(&bundles
, midgard_bundle
, bundle
);
1080 if (bundle
.has_blend_constant
)
1081 blend_offset
= block
->quadword_count
;
1083 block
->quadword_count
+= midgard_word_size
[bundle
.tag
];
1086 /* We emitted bundles backwards; copy into the block in reverse-order */
1088 util_dynarray_init(&block
->bundles
, block
);
1089 util_dynarray_foreach_reverse(&bundles
, midgard_bundle
, bundle
) {
1090 util_dynarray_append(&block
->bundles
, midgard_bundle
, *bundle
);
1092 util_dynarray_fini(&bundles
);
1094 /* Blend constant was backwards as well. blend_offset if set is
1095 * strictly positive, as an offset of zero would imply constants before
1096 * any instructions which is invalid in Midgard. TODO: blend constants
1097 * are broken if you spill since then quadword_count becomes invalid
1101 ctx
->blend_constant_offset
= ((ctx
->quadword_count
+ block
->quadword_count
) - blend_offset
- 1) * 0x10;
1103 block
->is_scheduled
= true;
1104 ctx
->quadword_count
+= block
->quadword_count
;
1106 /* Reorder instructions to match bundled. First remove existing
1107 * instructions and then recreate the list */
1109 mir_foreach_instr_in_block_safe(block
, ins
) {
1110 list_del(&ins
->link
);
1113 mir_foreach_instr_in_block_scheduled_rev(block
, ins
) {
1114 list_add(&ins
->link
, &block
->instructions
);
1117 free(instructions
); /* Allocated by flatten_mir() */
1122 midgard_schedule_program(compiler_context
*ctx
)
1124 midgard_promote_uniforms(ctx
);
1126 /* Must be lowered right before scheduling */
1127 mir_squeeze_index(ctx
);
1128 mir_lower_special_reads(ctx
);
1129 mir_squeeze_index(ctx
);
1131 /* Lowering can introduce some dead moves */
1133 mir_foreach_block(ctx
, block
) {
1134 midgard_opt_dead_move_eliminate(ctx
, block
);
1135 schedule_block(ctx
, block
);