src/panfrost/midgard/midgard_schedule.c

   1 /*
   2  * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  */
  23
  24 #include "compiler.h"
  25 #include "midgard_ops.h"
  26 #include "util/u_memory.h"
  27 #include "util/register_allocate.h"
  28
  29 /* Create a mask of accessed components from a swizzle to figure out vector
  30  * dependencies */
  31
  32 static unsigned
  33 swizzle_to_access_mask(unsigned swizzle)
  34 {
  35         unsigned component_mask = 0;
  36
  37         for (int i = 0; i < 4; ++i) {
  38                 unsigned c = (swizzle >> (2 * i)) & 3;
  39                 component_mask |= (1 << c);
  40         }
  41
  42         return component_mask;
  43 }
  44
  45 /* Does the mask cover more than a scalar? */
  46
  47 static bool
  48 is_single_component_mask(unsigned mask)
  49 {
  50         int components = 0;
  51
  52         for (int c = 0; c < 8; ++c) {
  53                 if (mask & (1 << c))
  54                         components++;
  55         }
  56
  57         return components == 1;
  58 }
  59
  60 /* Checks for an SSA data hazard between two adjacent instructions, keeping in
  61  * mind that we are a vector architecture and we can write to different
  62  * components simultaneously */
  63
  64 static bool
  65 can_run_concurrent_ssa(midgard_instruction *first, midgard_instruction *second)
  66 {
  67         /* Each instruction reads some registers and writes to a register. See
  68          * where the first writes */
  69
  70         /* Figure out where exactly we wrote to */
  71         int source = first->ssa_args.dest;
  72         int source_mask = first->mask;
  73
  74         /* As long as the second doesn't read from the first, we're okay */
  75         if (second->ssa_args.src0 == source) {
  76                 if (first->type == TAG_ALU_4) {
  77                         /* Figure out which components we just read from */
  78
  79                         int q = second->alu.src1;
  80                         midgard_vector_alu_src *m = (midgard_vector_alu_src *) &q;
  81
  82                         /* Check if there are components in common, and fail if so */
  83                         if (swizzle_to_access_mask(m->swizzle) & source_mask)
  84                                 return false;
  85                 } else
  86                         return false;
  87
  88         }
  89
  90         if (second->ssa_args.src1 == source)
  91                 return false;
  92
  93         /* Otherwise, it's safe in that regard. Another data hazard is both
  94          * writing to the same place, of course */
  95
  96         if (second->ssa_args.dest == source) {
  97                 /* ...but only if the components overlap */
  98
  99                 if (second->mask & source_mask)
 100                         return false;
 101         }
 102
 103         /* ...That's it */
 104         return true;
 105 }
 106
 107 static bool
 108 midgard_has_hazard(
 109         midgard_instruction **segment, unsigned segment_size,
 110         midgard_instruction *ains)
 111 {
 112         for (int s = 0; s < segment_size; ++s)
 113                 if (!can_run_concurrent_ssa(segment[s], ains))
 114                         return true;
 115
 116         return false;
 117
 118
 119 }
 120
 121 /* Schedules, but does not emit, a single basic block. After scheduling, the
 122  * final tag and size of the block are known, which are necessary for branching
 123  * */
 124
 125 static midgard_bundle
 126 schedule_bundle(compiler_context *ctx, midgard_block *block, midgard_instruction *ins, int *skip)
 127 {
 128         int instructions_emitted = 0, packed_idx = 0;
 129         midgard_bundle bundle = { 0 };
 130
 131         uint8_t tag = ins->type;
 132
 133         /* Default to the instruction's tag */
 134         bundle.tag = tag;
 135
 136         switch (ins->type) {
 137         case TAG_ALU_4: {
 138                 uint32_t control = 0;
 139                 size_t bytes_emitted = sizeof(control);
 140
 141                 /* TODO: Constant combining */
 142                 int index = 0, last_unit = 0;
 143
 144                 /* Previous instructions, for the purpose of parallelism */
 145                 midgard_instruction *segment[4] = {0};
 146                 int segment_size = 0;
 147
 148                 instructions_emitted = -1;
 149                 midgard_instruction *pins = ins;
 150
 151                 unsigned constant_count = 0;
 152
 153                 for (;;) {
 154                         midgard_instruction *ains = pins;
 155
 156                         /* Advance instruction pointer */
 157                         if (index) {
 158                                 ains = mir_next_op(pins);
 159                                 pins = ains;
 160                         }
 161
 162                         /* Out-of-work condition */
 163                         if ((struct list_head *) ains == &block->instructions)
 164                                 break;
 165
 166                         /* Ensure that the chain can continue */
 167                         if (ains->type != TAG_ALU_4) break;
 168
 169                         /* If there's already something in the bundle and we
 170                          * have weird scheduler constraints, break now */
 171                         if (ains->precede_break && index) break;
 172
 173                         /* According to the presentation "The ARM
 174                          * Mali-T880 Mobile GPU" from HotChips 27,
 175                          * there are two pipeline stages. Branching
 176                          * position determined experimentally. Lines
 177                          * are executed in parallel:
 178                          *
 179                          * [ VMUL ] [ SADD ]
 180                          * [ VADD ] [ SMUL ] [ LUT ] [ BRANCH ]
 181                          *
 182                          * Verify that there are no ordering dependencies here.
 183                          *
 184                          * TODO: Allow for parallelism!!!
 185                          */
 186
 187                         /* Pick a unit for it if it doesn't force a particular unit */
 188
 189                         int unit = ains->unit;
 190
 191                         if (!unit) {
 192                                 int op = ains->alu.op;
 193                                 int units = alu_opcode_props[op].props;
 194
 195                                 bool scalarable = units & UNITS_SCALAR;
 196                                 bool could_scalar = is_single_component_mask(ains->mask);
 197
 198                                 /* Only 16/32-bit can run on a scalar unit */
 199                                 could_scalar &= ains->alu.reg_mode != midgard_reg_mode_8;
 200                                 could_scalar &= ains->alu.reg_mode != midgard_reg_mode_64;
 201                                 could_scalar &= ains->alu.dest_override == midgard_dest_override_none;
 202
 203                                 if (ains->alu.reg_mode == midgard_reg_mode_16) {
 204                                         /* If we're running in 16-bit mode, we
 205                                          * can't have any 8-bit sources on the
 206                                          * scalar unit (since the scalar unit
 207                                          * doesn't understand 8-bit) */
 208
 209                                         midgard_vector_alu_src s1 =
 210                                                 vector_alu_from_unsigned(ains->alu.src1);
 211
 212                                         could_scalar &= !s1.half;
 213
 214                                         if (!ains->ssa_args.inline_constant) {
 215                                                 midgard_vector_alu_src s2 =
 216                                                         vector_alu_from_unsigned(ains->alu.src2);
 217
 218                                                 could_scalar &= !s2.half;
 219                                         }
 220
 221                                 }
 222
 223                                 bool scalar = could_scalar && scalarable;
 224
 225                                 /* TODO: Check ahead-of-time for other scalar
 226                                  * hazards that otherwise get aborted out */
 227
 228                                 if (scalar)
 229                                         assert(units & UNITS_SCALAR);
 230
 231                                 if (!scalar) {
 232                                         if (last_unit >= UNIT_VADD) {
 233                                                 if (units & UNIT_VLUT)
 234                                                         unit = UNIT_VLUT;
 235                                                 else
 236                                                         break;
 237                                         } else {
 238                                                 if ((units & UNIT_VMUL) && last_unit < UNIT_VMUL)
 239                                                         unit = UNIT_VMUL;
 240                                                 else if ((units & UNIT_VADD) && !(control & UNIT_VADD))
 241                                                         unit = UNIT_VADD;
 242                                                 else if (units & UNIT_VLUT)
 243                                                         unit = UNIT_VLUT;
 244                                                 else
 245                                                         break;
 246                                         }
 247                                 } else {
 248                                         if (last_unit >= UNIT_VADD) {
 249                                                 if ((units & UNIT_SMUL) && !(control & UNIT_SMUL))
 250                                                         unit = UNIT_SMUL;
 251                                                 else if (units & UNIT_VLUT)
 252                                                         unit = UNIT_VLUT;
 253                                                 else
 254                                                         break;
 255                                         } else {
 256                                                 if ((units & UNIT_SADD) && !(control & UNIT_SADD) && !midgard_has_hazard(segment, segment_size, ains))
 257                                                         unit = UNIT_SADD;
 258                                                 else if (units & UNIT_SMUL)
 259                                                         unit = ((units & UNIT_VMUL) && !(control & UNIT_VMUL)) ? UNIT_VMUL : UNIT_SMUL;
 260                                                 else if ((units & UNIT_VADD) && !(control & UNIT_VADD))
 261                                                         unit = UNIT_VADD;
 262                                                 else
 263                                                         break;
 264                                         }
 265                                 }
 266
 267                                 assert(unit & units);
 268                         }
 269
 270                         /* Late unit check, this time for encoding (not parallelism) */
 271                         if (unit <= last_unit) break;
 272
 273                         /* Clear the segment */
 274                         if (last_unit < UNIT_VADD && unit >= UNIT_VADD)
 275                                 segment_size = 0;
 276
 277                         if (midgard_has_hazard(segment, segment_size, ains))
 278                                 break;
 279
 280                         /* We're good to go -- emit the instruction */
 281                         ains->unit = unit;
 282
 283                         segment[segment_size++] = ains;
 284
 285                         /* We try to reuse constants if possible, by adjusting
 286                          * the swizzle */
 287
 288                         if (ains->has_blend_constant) {
 289                                 /* Everything conflicts with the blend constant */
 290                                 if (bundle.has_embedded_constants)
 291                                         break;
 292
 293                                 bundle.has_blend_constant = 1;
 294                                 bundle.has_embedded_constants = 1;
 295                         } else if (ains->has_constants && ains->alu.reg_mode == midgard_reg_mode_16) {
 296                                 /* TODO: DRY with the analysis pass */
 297
 298                                 if (bundle.has_blend_constant)
 299                                         break;
 300
 301                                 if (constant_count)
 302                                         break;
 303
 304                                 /* TODO: Fix packing XXX */
 305                                 uint16_t *bundles = (uint16_t *) bundle.constants;
 306                                 uint32_t *constants = (uint32_t *) ains->constants;
 307
 308                                 /* Copy them wholesale */
 309                                 for (unsigned i = 0; i < 4; ++i)
 310                                         bundles[i] = constants[i];
 311
 312                                 bundle.has_embedded_constants = true;
 313                                 constant_count = 4;
 314                         } else if (ains->has_constants) {
 315                                 /* By definition, blend constants conflict with
 316                                  * everything, so if there are already
 317                                  * constants we break the bundle *now* */
 318
 319                                 if (bundle.has_blend_constant)
 320                                         break;
 321
 322                                 /* For anything but blend constants, we can do
 323                                  * proper analysis, however */
 324
 325                                 /* TODO: Mask by which are used */
 326                                 uint32_t *constants = (uint32_t *) ains->constants;
 327                                 uint32_t *bundles = (uint32_t *) bundle.constants;
 328
 329                                 uint32_t indices[4] = { 0 };
 330                                 bool break_bundle = false;
 331
 332                                 for (unsigned i = 0; i < 4; ++i) {
 333                                         uint32_t cons = constants[i];
 334                                         bool constant_found = false;
 335
 336                                         /* Search for the constant */
 337                                         for (unsigned j = 0; j < constant_count; ++j) {
 338                                                 if (bundles[j] != cons)
 339                                                         continue;
 340
 341                                                 /* We found it, reuse */
 342                                                 indices[i] = j;
 343                                                 constant_found = true;
 344                                                 break;
 345                                         }
 346
 347                                         if (constant_found)
 348                                                 continue;
 349
 350                                         /* We didn't find it, so allocate it */
 351                                         unsigned idx = constant_count++;
 352
 353                                         if (idx >= 4) {
 354                                                 /* Uh-oh, out of space */
 355                                                 break_bundle = true;
 356                                                 break;
 357                                         }
 358
 359                                         /* We have space, copy it in! */
 360                                         bundles[idx] = cons;
 361                                         indices[i] = idx;
 362                                 }
 363
 364                                 if (break_bundle)
 365                                         break;
 366
 367                                 /* Cool, we have it in. So use indices as a
 368                                  * swizzle */
 369
 370                                 unsigned swizzle = SWIZZLE_FROM_ARRAY(indices);
 371                                 unsigned r_constant = SSA_FIXED_REGISTER(REGISTER_CONSTANT);
 372
 373                                 if (ains->ssa_args.src0 == r_constant)
 374                                         ains->alu.src1 = vector_alu_apply_swizzle(ains->alu.src1, swizzle);
 375
 376                                 if (ains->ssa_args.src1 == r_constant)
 377                                         ains->alu.src2 = vector_alu_apply_swizzle(ains->alu.src2, swizzle);
 378
 379                                 bundle.has_embedded_constants = true;
 380                         }
 381
 382                         if (ains->unit & UNITS_ANY_VECTOR) {
 383                                 bytes_emitted += sizeof(midgard_reg_info);
 384                                 bytes_emitted += sizeof(midgard_vector_alu);
 385                         } else if (ains->compact_branch) {
 386                                 /* All of r0 has to be written out along with
 387                                  * the branch writeout */
 388
 389                                 if (ains->writeout) {
 390                                         /* The rules for when "bare" writeout
 391                                          * is safe are when all components are
 392                                          * r0 are written out in the final
 393                                          * bundle, earlier than VLUT, where any
 394                                          * register dependencies of r0 are from
 395                                          * an earlier bundle. We can't verify
 396                                          * this before RA, so we don't try. */
 397
 398                                         if (index != 0)
 399                                                 break;
 400
 401                                         /* Inject a move */
 402                                         midgard_instruction ins = v_mov(0, blank_alu_src, SSA_FIXED_REGISTER(0));
 403                                         ins.unit = UNIT_VMUL;
 404                                         control |= ins.unit;
 405
 406                                         /* TODO don't leak */
 407                                         midgard_instruction *move =
 408                                                 mem_dup(&ins, sizeof(midgard_instruction));
 409                                         bytes_emitted += sizeof(midgard_reg_info);
 410                                         bytes_emitted += sizeof(midgard_vector_alu);
 411                                         bundle.instructions[packed_idx++] = move;
 412                                 }
 413
 414                                 if (ains->unit == ALU_ENAB_BRANCH) {
 415                                         bytes_emitted += sizeof(midgard_branch_extended);
 416                                 } else {
 417                                         bytes_emitted += sizeof(ains->br_compact);
 418                                 }
 419                         } else {
 420                                 bytes_emitted += sizeof(midgard_reg_info);
 421                                 bytes_emitted += sizeof(midgard_scalar_alu);
 422                         }
 423
 424                         /* Defer marking until after writing to allow for break */
 425                         control |= ains->unit;
 426                         last_unit = ains->unit;
 427                         ++instructions_emitted;
 428                         ++index;
 429                 }
 430
 431                 int padding = 0;
 432
 433                 /* Pad ALU op to nearest word */
 434
 435                 if (bytes_emitted & 15) {
 436                         padding = 16 - (bytes_emitted & 15);
 437                         bytes_emitted += padding;
 438                 }
 439
 440                 /* Constants must always be quadwords */
 441                 if (bundle.has_embedded_constants)
 442                         bytes_emitted += 16;
 443
 444                 /* Size ALU instruction for tag */
 445                 bundle.tag = (TAG_ALU_4) + (bytes_emitted / 16) - 1;
 446                 bundle.padding = padding;
 447                 bundle.control = bundle.tag | control;
 448
 449                 break;
 450         }
 451
 452         case TAG_LOAD_STORE_4: {
 453                 /* Load store instructions have two words at once. If
 454                  * we only have one queued up, we need to NOP pad.
 455                  * Otherwise, we store both in succession to save space
 456                  * and cycles -- letting them go in parallel -- skip
 457                  * the next. The usefulness of this optimisation is
 458                  * greatly dependent on the quality of the instruction
 459                  * scheduler.
 460                  */
 461
 462                 midgard_instruction *next_op = mir_next_op(ins);
 463
 464                 if ((struct list_head *) next_op != &block->instructions && next_op->type == TAG_LOAD_STORE_4) {
 465                         /* TODO: Concurrency check */
 466                         instructions_emitted++;
 467                 }
 468
 469                 break;
 470         }
 471
 472         case TAG_TEXTURE_4: {
 473                 /* Which tag we use depends on the shader stage */
 474                 bool in_frag = ctx->stage == MESA_SHADER_FRAGMENT;
 475                 bundle.tag = in_frag ? TAG_TEXTURE_4 : TAG_TEXTURE_4_VTX;
 476                 break;
 477         }
 478
 479         default:
 480                 unreachable("Unknown tag");
 481                 break;
 482         }
 483
 484         /* Copy the instructions into the bundle */
 485         bundle.instruction_count = instructions_emitted + 1 + packed_idx;
 486
 487         midgard_instruction *uins = ins;
 488         for (; packed_idx < bundle.instruction_count; ++packed_idx) {
 489                 bundle.instructions[packed_idx] = uins;
 490                 uins = mir_next_op(uins);
 491         }
 492
 493         *skip = instructions_emitted;
 494
 495         return bundle;
 496 }
 497
 498 /* Schedule a single block by iterating its instruction to create bundles.
 499  * While we go, tally about the bundle sizes to compute the block size. */
 500
 501 static void
 502 schedule_block(compiler_context *ctx, midgard_block *block)
 503 {
 504         util_dynarray_init(&block->bundles, NULL);
 505
 506         block->quadword_count = 0;
 507
 508         mir_foreach_instr_in_block(block, ins) {
 509                 int skip;
 510                 midgard_bundle bundle = schedule_bundle(ctx, block, ins, &skip);
 511                 util_dynarray_append(&block->bundles, midgard_bundle, bundle);
 512
 513                 if (bundle.has_blend_constant) {
 514                         /* TODO: Multiblock? */
 515                         int quadwords_within_block = block->quadword_count + quadword_size(bundle.tag) - 1;
 516                         ctx->blend_constant_offset = quadwords_within_block * 0x10;
 517                 }
 518
 519                 while(skip--)
 520                         ins = mir_next_op(ins);
 521
 522                 block->quadword_count += quadword_size(bundle.tag);
 523         }
 524
 525         block->is_scheduled = true;
 526 }
 527
 528 /* The following passes reorder MIR instructions to enable better scheduling */
 529
 530 static void
 531 midgard_pair_load_store(compiler_context *ctx, midgard_block *block)
 532 {
 533         mir_foreach_instr_in_block_safe(block, ins) {
 534                 if (ins->type != TAG_LOAD_STORE_4) continue;
 535
 536                 /* We've found a load/store op. Check if next is also load/store. */
 537                 midgard_instruction *next_op = mir_next_op(ins);
 538                 if (&next_op->link != &block->instructions) {
 539                         if (next_op->type == TAG_LOAD_STORE_4) {
 540                                 /* If so, we're done since we're a pair */
 541                                 ins = mir_next_op(ins);
 542                                 continue;
 543                         }
 544
 545                         /* Maximum search distance to pair, to avoid register pressure disasters */
 546                         int search_distance = 8;
 547
 548                         /* Otherwise, we have an orphaned load/store -- search for another load */
 549                         mir_foreach_instr_in_block_from(block, c, mir_next_op(ins)) {
 550                                 /* Terminate search if necessary */
 551                                 if (!(search_distance--)) break;
 552
 553                                 if (c->type != TAG_LOAD_STORE_4) continue;
 554
 555                                 /* Stores cannot be reordered, since they have
 556                                  * dependencies. For the same reason, indirect
 557                                  * loads cannot be reordered as their index is
 558                                  * loaded in r27.w */
 559
 560                                 if (OP_IS_STORE(c->load_store.op)) continue;
 561
 562                                 /* It appears the 0x800 bit is set whenever a
 563                                  * load is direct, unset when it is indirect.
 564                                  * Skip indirect loads. */
 565
 566                                 if (!(c->load_store.unknown & 0x800)) continue;
 567
 568                                 /* We found one! Move it up to pair and remove it from the old location */
 569
 570                                 mir_insert_instruction_before(ins, *c);
 571                                 mir_remove_instruction(c);
 572
 573                                 break;
 574                         }
 575                 }
 576         }
 577 }
 578
 579 /* When we're 'squeezing down' the values in the IR, we maintain a hash
 580  * as such */
 581
 582 static unsigned
 583 find_or_allocate_temp(compiler_context *ctx, unsigned hash)
 584 {
 585         if ((hash < 0) || (hash >= SSA_FIXED_MINIMUM))
 586                 return hash;
 587
 588         unsigned temp = (uintptr_t) _mesa_hash_table_u64_search(
 589                                 ctx->hash_to_temp, hash + 1);
 590
 591         if (temp)
 592                 return temp - 1;
 593
 594         /* If no temp is find, allocate one */
 595         temp = ctx->temp_count++;
 596         ctx->max_hash = MAX2(ctx->max_hash, hash);
 597
 598         _mesa_hash_table_u64_insert(ctx->hash_to_temp,
 599                                     hash + 1, (void *) ((uintptr_t) temp + 1));
 600
 601         return temp;
 602 }
 603
 604 /* Reassigns numbering to get rid of gaps in the indices */
 605
 606 static void
 607 mir_squeeze_index(compiler_context *ctx)
 608 {
 609         /* Reset */
 610         ctx->temp_count = 0;
 611         /* TODO don't leak old hash_to_temp */
 612         ctx->hash_to_temp = _mesa_hash_table_u64_create(NULL);
 613
 614         mir_foreach_instr_global(ctx, ins) {
 615                 if (ins->compact_branch) continue;
 616
 617                 ins->ssa_args.dest = find_or_allocate_temp(ctx, ins->ssa_args.dest);
 618                 ins->ssa_args.src0 = find_or_allocate_temp(ctx, ins->ssa_args.src0);
 619
 620                 if (!ins->ssa_args.inline_constant)
 621                         ins->ssa_args.src1 = find_or_allocate_temp(ctx, ins->ssa_args.src1);
 622
 623         }
 624 }
 625
 626 static midgard_instruction
 627 v_load_store_scratch(
 628                 unsigned srcdest,
 629                 unsigned index,
 630                 bool is_store,
 631                 unsigned mask)
 632 {
 633         /* We index by 32-bit vec4s */
 634         unsigned byte = (index * 4 * 4);
 635
 636         midgard_instruction ins = {
 637                 .type = TAG_LOAD_STORE_4,
 638                 .mask = mask,
 639                 .ssa_args = {
 640                         .dest = -1,
 641                         .src0 = -1,
 642                         .src1 = -1
 643                 },
 644                 .load_store = {
 645                         .op = is_store ? midgard_op_st_int4 : midgard_op_ld_int4,
 646                         .swizzle = SWIZZLE_XYZW,
 647
 648                         /* For register spilling - to thread local storage */
 649                         .unknown = 0x1EEA,
 650
 651                         /* Splattered across, TODO combine logically */
 652                         .varying_parameters = (byte & 0x1FF) << 1,
 653                         .address = (byte >> 9)
 654                 }
 655         };
 656
 657        if (is_store) {
 658                 /* r0 = r26, r1 = r27 */
 659                 assert(srcdest == SSA_FIXED_REGISTER(26) || srcdest == SSA_FIXED_REGISTER(27));
 660                 ins.ssa_args.src0 = (srcdest == SSA_FIXED_REGISTER(27)) ? SSA_FIXED_REGISTER(1) : SSA_FIXED_REGISTER(0);
 661         } else {
 662                 ins.ssa_args.dest = srcdest;
 663         }
 664
 665         return ins;
 666 }
 667
 668 void
 669 schedule_program(compiler_context *ctx)
 670 {
 671         struct ra_graph *g = NULL;
 672         bool spilled = false;
 673         int iter_count = 1000; /* max iterations */
 674
 675         /* Number of 128-bit slots in memory we've spilled into */
 676         unsigned spill_count = 0;
 677
 678         midgard_promote_uniforms(ctx, 8);
 679
 680         mir_foreach_block(ctx, block) {
 681                 midgard_pair_load_store(ctx, block);
 682         }
 683
 684         do {
 685                 /* If we spill, find the best spill node and spill it */
 686
 687                 unsigned spill_index = ctx->temp_count;
 688                 if (g && spilled) {
 689                         /* All nodes are equal in spill cost, but we can't
 690                          * spill nodes written to from an unspill */
 691
 692                         for (unsigned i = 0; i < ctx->temp_count; ++i) {
 693                                 ra_set_node_spill_cost(g, i, 1.0);
 694                         }
 695
 696                         mir_foreach_instr_global(ctx, ins) {
 697                                 if (ins->type != TAG_LOAD_STORE_4)  continue;
 698                                 if (ins->load_store.op != midgard_op_ld_int4) continue;
 699                                 if (ins->load_store.unknown != 0x1EEA) continue;
 700                                 ra_set_node_spill_cost(g, ins->ssa_args.dest, -1.0);
 701                         }
 702
 703                         int spill_node = ra_get_best_spill_node(g);
 704
 705                         if (spill_node < 0) {
 706                                 mir_print_shader(ctx);
 707                                 assert(0);
 708                         }
 709
 710                         /* Allocate TLS slot */
 711                         unsigned spill_slot = spill_count++;
 712
 713                         /* Replace all stores to the spilled node with stores
 714                          * to TLS */
 715
 716                         mir_foreach_instr_global_safe(ctx, ins) {
 717                                 if (ins->compact_branch) continue;
 718                                 if (ins->ssa_args.dest != spill_node) continue;
 719                                 ins->ssa_args.dest = SSA_FIXED_REGISTER(26);
 720
 721                                 midgard_instruction st = v_load_store_scratch(ins->ssa_args.dest, spill_slot, true, ins->mask);
 722                                 mir_insert_instruction_before(mir_next_op(ins), st);
 723
 724                                 ctx->spills++;
 725                         }
 726
 727                         /* Insert a load from TLS before the first consecutive
 728                          * use of the node, rewriting to use spilled indices to
 729                          * break up the live range */
 730
 731                         mir_foreach_block(ctx, block) {
 732
 733                         bool consecutive_skip = false;
 734                         unsigned consecutive_index = 0;
 735
 736                         mir_foreach_instr_in_block(block, ins) {
 737                                 if (ins->compact_branch) continue;
 738
 739                                 if (!mir_has_arg(ins, spill_node)) {
 740                                         consecutive_skip = false;
 741                                         continue;
 742                                 }
 743
 744                                 if (consecutive_skip) {
 745                                         /* Rewrite */
 746                                         mir_rewrite_index_src_single(ins, spill_node, consecutive_index);
 747                                         continue;
 748                                 }
 749
 750                                 consecutive_index = ++spill_index;
 751                                 midgard_instruction st = v_load_store_scratch(consecutive_index, spill_slot, false, 0xF);
 752                                 midgard_instruction *before = ins;
 753
 754                                 /* For a csel, go back one more not to break up the bundle */
 755                                 if (ins->type == TAG_ALU_4 && OP_IS_CSEL(ins->alu.op))
 756                                         before = mir_prev_op(before);
 757
 758                                 mir_insert_instruction_before(before, st);
 759                                // consecutive_skip = true;
 760
 761
 762                                 /* Rewrite to use */
 763                                 mir_rewrite_index_src_single(ins, spill_node, consecutive_index);
 764
 765                                 ctx->fills++;
 766                         }
 767                         }
 768                 }
 769
 770                 mir_squeeze_index(ctx);
 771
 772                 g = NULL;
 773                 g = allocate_registers(ctx, &spilled);
 774         } while(spilled && ((iter_count--) > 0));
 775
 776         /* After RA finishes, we schedule all at once */
 777
 778         mir_foreach_block(ctx, block) {
 779                 schedule_block(ctx, block);
 780         }
 781
 782         /* Finally, we create pipeline registers as a peephole pass after
 783          * scheduling. This isn't totally optimal, since there are cases where
 784          * the usage of pipeline registers can eliminate spills, but it does
 785          * save some power */
 786
 787         mir_create_pipeline_registers(ctx);
 788
 789         if (iter_count <= 0) {
 790                 fprintf(stderr, "panfrost: Gave up allocating registers, rendering will be incomplete\n");
 791                 assert(0);
 792         }
 793
 794         /* Report spilling information. spill_count is in 128-bit slots (vec4 x
 795          * fp32), but tls_size is in bytes, so multiply by 16 */
 796
 797         ctx->tls_size = spill_count * 16;
 798
 799         install_registers(ctx, g);
 800 }