2 * Copyright (C) 2018-2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 #include "midgard_ops.h"
26 #include "util/u_memory.h"
27 #include "util/register_allocate.h"
29 /* Create a mask of accessed components from a swizzle to figure out vector
33 swizzle_to_access_mask(unsigned swizzle
)
35 unsigned component_mask
= 0;
37 for (int i
= 0; i
< 4; ++i
) {
38 unsigned c
= (swizzle
>> (2 * i
)) & 3;
39 component_mask
|= (1 << c
);
42 return component_mask
;
45 /* Does the mask cover more than a scalar? */
48 is_single_component_mask(unsigned mask
)
52 for (int c
= 0; c
< 8; ++c
) {
57 return components
== 1;
60 /* Checks for an SSA data hazard between two adjacent instructions, keeping in
61 * mind that we are a vector architecture and we can write to different
62 * components simultaneously */
65 can_run_concurrent_ssa(midgard_instruction
*first
, midgard_instruction
*second
)
67 /* Each instruction reads some registers and writes to a register. See
68 * where the first writes */
70 /* Figure out where exactly we wrote to */
71 int source
= first
->ssa_args
.dest
;
72 int source_mask
= first
->mask
;
74 /* As long as the second doesn't read from the first, we're okay */
75 if (second
->ssa_args
.src0
== source
) {
76 if (first
->type
== TAG_ALU_4
) {
77 /* Figure out which components we just read from */
79 int q
= second
->alu
.src1
;
80 midgard_vector_alu_src
*m
= (midgard_vector_alu_src
*) &q
;
82 /* Check if there are components in common, and fail if so */
83 if (swizzle_to_access_mask(m
->swizzle
) & source_mask
)
90 if (second
->ssa_args
.src1
== source
)
93 /* Otherwise, it's safe in that regard. Another data hazard is both
94 * writing to the same place, of course */
96 if (second
->ssa_args
.dest
== source
) {
97 /* ...but only if the components overlap */
99 if (second
->mask
& source_mask
)
109 midgard_instruction
**segment
, unsigned segment_size
,
110 midgard_instruction
*ains
)
112 for (int s
= 0; s
< segment_size
; ++s
)
113 if (!can_run_concurrent_ssa(segment
[s
], ains
))
121 /* Fragment writeout (of r0) is allowed when:
123 * - All components of r0 are written in the bundle
124 * - No components of r0 are written in VLUT
125 * - Non-pipelined dependencies of r0 are not written in the bundle
127 * This function checks if these requirements are satisfied given the content
128 * of a scheduled bundle.
132 can_writeout_fragment(compiler_context
*ctx
, midgard_instruction
**bundle
, unsigned count
, unsigned node_count
)
134 /* First scan for which components of r0 are written out. Initially
135 * none are written */
137 uint8_t r0_written_mask
= 0x0;
139 /* Simultaneously we scan for the set of dependencies */
140 BITSET_WORD
*dependencies
= calloc(sizeof(BITSET_WORD
), BITSET_WORDS(node_count
));
142 for (unsigned i
= 0; i
< count
; ++i
) {
143 midgard_instruction
*ins
= bundle
[i
];
145 if (ins
->ssa_args
.dest
!= SSA_FIXED_REGISTER(0))
148 /* Record written out mask */
149 r0_written_mask
|= ins
->mask
;
151 /* Record dependencies, but only if they won't become pipeline
152 * registers. We know we can't be live after this, because
153 * we're writeout at the very end of the shader. So check if
154 * they were written before us. */
156 unsigned src0
= ins
->ssa_args
.src0
;
157 unsigned src1
= ins
->ssa_args
.src1
;
159 if (!mir_is_written_before(ctx
, bundle
[0], src0
))
162 if (!mir_is_written_before(ctx
, bundle
[0], src1
))
165 if ((src0
> 0) && (src0
< node_count
))
166 BITSET_SET(dependencies
, src0
);
168 if ((src1
> 0) && (src1
< node_count
))
169 BITSET_SET(dependencies
, src1
);
172 if (ins
->unit
== UNIT_VLUT
)
177 if ((r0_written_mask
& 0xF) != 0xF)
182 for (unsigned i
= 0; i
< count
; ++i
) {
183 unsigned dest
= bundle
[i
]->ssa_args
.dest
;
185 if (dest
< node_count
&& BITSET_TEST(dependencies
, dest
))
189 /* Otherwise, we're good to go */
193 /* Schedules, but does not emit, a single basic block. After scheduling, the
194 * final tag and size of the block are known, which are necessary for branching
197 static midgard_bundle
198 schedule_bundle(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*ins
, int *skip
)
200 int instructions_emitted
= 0, packed_idx
= 0;
201 midgard_bundle bundle
= { 0 };
203 midgard_instruction
*scheduled
[5] = { NULL
};
205 uint8_t tag
= ins
->type
;
207 /* Default to the instruction's tag */
212 uint32_t control
= 0;
213 size_t bytes_emitted
= sizeof(control
);
215 /* TODO: Constant combining */
216 int index
= 0, last_unit
= 0;
218 /* Previous instructions, for the purpose of parallelism */
219 midgard_instruction
*segment
[4] = {0};
220 int segment_size
= 0;
222 instructions_emitted
= -1;
223 midgard_instruction
*pins
= ins
;
225 unsigned constant_count
= 0;
228 midgard_instruction
*ains
= pins
;
230 /* Advance instruction pointer */
232 ains
= mir_next_op(pins
);
236 /* Out-of-work condition */
237 if ((struct list_head
*) ains
== &block
->instructions
)
240 /* Ensure that the chain can continue */
241 if (ains
->type
!= TAG_ALU_4
) break;
243 /* If there's already something in the bundle and we
244 * have weird scheduler constraints, break now */
245 if (ains
->precede_break
&& index
) break;
247 /* According to the presentation "The ARM
248 * Mali-T880 Mobile GPU" from HotChips 27,
249 * there are two pipeline stages. Branching
250 * position determined experimentally. Lines
251 * are executed in parallel:
254 * [ VADD ] [ SMUL ] [ LUT ] [ BRANCH ]
256 * Verify that there are no ordering dependencies here.
258 * TODO: Allow for parallelism!!!
261 /* Pick a unit for it if it doesn't force a particular unit */
263 int unit
= ains
->unit
;
266 int op
= ains
->alu
.op
;
267 int units
= alu_opcode_props
[op
].props
;
269 bool scalarable
= units
& UNITS_SCALAR
;
270 bool could_scalar
= is_single_component_mask(ains
->mask
);
272 /* Only 16/32-bit can run on a scalar unit */
273 could_scalar
&= ains
->alu
.reg_mode
!= midgard_reg_mode_8
;
274 could_scalar
&= ains
->alu
.reg_mode
!= midgard_reg_mode_64
;
275 could_scalar
&= ains
->alu
.dest_override
== midgard_dest_override_none
;
277 if (ains
->alu
.reg_mode
== midgard_reg_mode_16
) {
278 /* If we're running in 16-bit mode, we
279 * can't have any 8-bit sources on the
280 * scalar unit (since the scalar unit
281 * doesn't understand 8-bit) */
283 midgard_vector_alu_src s1
=
284 vector_alu_from_unsigned(ains
->alu
.src1
);
286 could_scalar
&= !s1
.half
;
288 if (!ains
->ssa_args
.inline_constant
) {
289 midgard_vector_alu_src s2
=
290 vector_alu_from_unsigned(ains
->alu
.src2
);
292 could_scalar
&= !s2
.half
;
297 bool scalar
= could_scalar
&& scalarable
;
299 /* TODO: Check ahead-of-time for other scalar
300 * hazards that otherwise get aborted out */
303 assert(units
& UNITS_SCALAR
);
306 if (last_unit
>= UNIT_VADD
) {
307 if (units
& UNIT_VLUT
)
312 if ((units
& UNIT_VMUL
) && last_unit
< UNIT_VMUL
)
314 else if ((units
& UNIT_VADD
) && !(control
& UNIT_VADD
))
316 else if (units
& UNIT_VLUT
)
322 if (last_unit
>= UNIT_VADD
) {
323 if ((units
& UNIT_SMUL
) && !(control
& UNIT_SMUL
))
325 else if (units
& UNIT_VLUT
)
330 if ((units
& UNIT_VMUL
) && (last_unit
< UNIT_VMUL
))
332 else if ((units
& UNIT_SADD
) && !(control
& UNIT_SADD
) && !midgard_has_hazard(segment
, segment_size
, ains
))
334 else if (units
& UNIT_VADD
)
336 else if (units
& UNIT_SMUL
)
338 else if (units
& UNIT_VLUT
)
345 assert(unit
& units
);
348 /* Late unit check, this time for encoding (not parallelism) */
349 if (unit
<= last_unit
) break;
351 /* Clear the segment */
352 if (last_unit
< UNIT_VADD
&& unit
>= UNIT_VADD
)
355 if (midgard_has_hazard(segment
, segment_size
, ains
))
358 /* We're good to go -- emit the instruction */
361 segment
[segment_size
++] = ains
;
363 /* We try to reuse constants if possible, by adjusting
366 if (ains
->has_blend_constant
) {
367 /* Everything conflicts with the blend constant */
368 if (bundle
.has_embedded_constants
)
371 bundle
.has_blend_constant
= 1;
372 bundle
.has_embedded_constants
= 1;
373 } else if (ains
->has_constants
&& ains
->alu
.reg_mode
== midgard_reg_mode_16
) {
374 /* TODO: DRY with the analysis pass */
376 if (bundle
.has_blend_constant
)
382 /* TODO: Fix packing XXX */
383 uint16_t *bundles
= (uint16_t *) bundle
.constants
;
384 uint32_t *constants
= (uint32_t *) ains
->constants
;
386 /* Copy them wholesale */
387 for (unsigned i
= 0; i
< 4; ++i
)
388 bundles
[i
] = constants
[i
];
390 bundle
.has_embedded_constants
= true;
392 } else if (ains
->has_constants
) {
393 /* By definition, blend constants conflict with
394 * everything, so if there are already
395 * constants we break the bundle *now* */
397 if (bundle
.has_blend_constant
)
400 /* For anything but blend constants, we can do
401 * proper analysis, however */
403 /* TODO: Mask by which are used */
404 uint32_t *constants
= (uint32_t *) ains
->constants
;
405 uint32_t *bundles
= (uint32_t *) bundle
.constants
;
407 uint32_t indices
[4] = { 0 };
408 bool break_bundle
= false;
410 for (unsigned i
= 0; i
< 4; ++i
) {
411 uint32_t cons
= constants
[i
];
412 bool constant_found
= false;
414 /* Search for the constant */
415 for (unsigned j
= 0; j
< constant_count
; ++j
) {
416 if (bundles
[j
] != cons
)
419 /* We found it, reuse */
421 constant_found
= true;
428 /* We didn't find it, so allocate it */
429 unsigned idx
= constant_count
++;
432 /* Uh-oh, out of space */
437 /* We have space, copy it in! */
445 /* Cool, we have it in. So use indices as a
448 unsigned swizzle
= SWIZZLE_FROM_ARRAY(indices
);
449 unsigned r_constant
= SSA_FIXED_REGISTER(REGISTER_CONSTANT
);
451 if (ains
->ssa_args
.src0
== r_constant
)
452 ains
->alu
.src1
= vector_alu_apply_swizzle(ains
->alu
.src1
, swizzle
);
454 if (ains
->ssa_args
.src1
== r_constant
)
455 ains
->alu
.src2
= vector_alu_apply_swizzle(ains
->alu
.src2
, swizzle
);
457 bundle
.has_embedded_constants
= true;
460 if (ains
->unit
& UNITS_ANY_VECTOR
) {
461 bytes_emitted
+= sizeof(midgard_reg_info
);
462 bytes_emitted
+= sizeof(midgard_vector_alu
);
463 } else if (ains
->compact_branch
) {
464 /* All of r0 has to be written out along with
465 * the branch writeout */
467 unsigned node_count
= ctx
->func
->impl
->ssa_alloc
+ ctx
->func
->impl
->reg_alloc
;
469 if (ains
->writeout
&& !can_writeout_fragment(ctx
, scheduled
, index
, node_count
)) {
470 /* We only work on full moves
471 * at the beginning. We could
472 * probably do better */
477 midgard_instruction ins
= v_mov(0, blank_alu_src
, SSA_FIXED_REGISTER(0));
478 ins
.unit
= UNIT_VMUL
;
481 /* TODO don't leak */
482 midgard_instruction
*move
=
483 mem_dup(&ins
, sizeof(midgard_instruction
));
484 bytes_emitted
+= sizeof(midgard_reg_info
);
485 bytes_emitted
+= sizeof(midgard_vector_alu
);
486 bundle
.instructions
[packed_idx
++] = move
;
489 if (ains
->unit
== ALU_ENAB_BRANCH
) {
490 bytes_emitted
+= sizeof(midgard_branch_extended
);
492 bytes_emitted
+= sizeof(ains
->br_compact
);
495 bytes_emitted
+= sizeof(midgard_reg_info
);
496 bytes_emitted
+= sizeof(midgard_scalar_alu
);
499 /* Defer marking until after writing to allow for break */
500 scheduled
[index
] = ains
;
501 control
|= ains
->unit
;
502 last_unit
= ains
->unit
;
503 ++instructions_emitted
;
509 /* Pad ALU op to nearest word */
511 if (bytes_emitted
& 15) {
512 padding
= 16 - (bytes_emitted
& 15);
513 bytes_emitted
+= padding
;
516 /* Constants must always be quadwords */
517 if (bundle
.has_embedded_constants
)
520 /* Size ALU instruction for tag */
521 bundle
.tag
= (TAG_ALU_4
) + (bytes_emitted
/ 16) - 1;
522 bundle
.padding
= padding
;
523 bundle
.control
= bundle
.tag
| control
;
528 case TAG_LOAD_STORE_4
: {
529 /* Load store instructions have two words at once. If
530 * we only have one queued up, we need to NOP pad.
531 * Otherwise, we store both in succession to save space
532 * and cycles -- letting them go in parallel -- skip
533 * the next. The usefulness of this optimisation is
534 * greatly dependent on the quality of the instruction
538 midgard_instruction
*next_op
= mir_next_op(ins
);
540 if ((struct list_head
*) next_op
!= &block
->instructions
&& next_op
->type
== TAG_LOAD_STORE_4
) {
541 /* TODO: Concurrency check */
542 instructions_emitted
++;
548 case TAG_TEXTURE_4
: {
549 /* Which tag we use depends on the shader stage */
550 bool in_frag
= ctx
->stage
== MESA_SHADER_FRAGMENT
;
551 bundle
.tag
= in_frag
? TAG_TEXTURE_4
: TAG_TEXTURE_4_VTX
;
556 unreachable("Unknown tag");
560 /* Copy the instructions into the bundle */
561 bundle
.instruction_count
= instructions_emitted
+ 1 + packed_idx
;
563 midgard_instruction
*uins
= ins
;
564 for (; packed_idx
< bundle
.instruction_count
; ++packed_idx
) {
565 bundle
.instructions
[packed_idx
] = uins
;
566 uins
= mir_next_op(uins
);
569 *skip
= instructions_emitted
;
574 /* Schedule a single block by iterating its instruction to create bundles.
575 * While we go, tally about the bundle sizes to compute the block size. */
578 schedule_block(compiler_context
*ctx
, midgard_block
*block
)
580 util_dynarray_init(&block
->bundles
, NULL
);
582 block
->quadword_count
= 0;
584 mir_foreach_instr_in_block(block
, ins
) {
586 midgard_bundle bundle
= schedule_bundle(ctx
, block
, ins
, &skip
);
587 util_dynarray_append(&block
->bundles
, midgard_bundle
, bundle
);
589 if (bundle
.has_blend_constant
) {
590 /* TODO: Multiblock? */
591 int quadwords_within_block
= block
->quadword_count
+ quadword_size(bundle
.tag
) - 1;
592 ctx
->blend_constant_offset
= quadwords_within_block
* 0x10;
596 ins
= mir_next_op(ins
);
598 block
->quadword_count
+= quadword_size(bundle
.tag
);
601 block
->is_scheduled
= true;
604 /* The following passes reorder MIR instructions to enable better scheduling */
607 midgard_pair_load_store(compiler_context
*ctx
, midgard_block
*block
)
609 mir_foreach_instr_in_block_safe(block
, ins
) {
610 if (ins
->type
!= TAG_LOAD_STORE_4
) continue;
612 /* We've found a load/store op. Check if next is also load/store. */
613 midgard_instruction
*next_op
= mir_next_op(ins
);
614 if (&next_op
->link
!= &block
->instructions
) {
615 if (next_op
->type
== TAG_LOAD_STORE_4
) {
616 /* If so, we're done since we're a pair */
617 ins
= mir_next_op(ins
);
621 /* Maximum search distance to pair, to avoid register pressure disasters */
622 int search_distance
= 8;
624 /* Otherwise, we have an orphaned load/store -- search for another load */
625 mir_foreach_instr_in_block_from(block
, c
, mir_next_op(ins
)) {
626 /* Terminate search if necessary */
627 if (!(search_distance
--)) break;
629 if (c
->type
!= TAG_LOAD_STORE_4
) continue;
631 /* Stores cannot be reordered, since they have
632 * dependencies. For the same reason, indirect
633 * loads cannot be reordered as their index is
636 if (OP_IS_STORE(c
->load_store
.op
)) continue;
638 /* It appears the 0x800 bit is set whenever a
639 * load is direct, unset when it is indirect.
640 * Skip indirect loads. */
642 if (!(c
->load_store
.unknown
& 0x800)) continue;
644 /* We found one! Move it up to pair and remove it from the old location */
646 mir_insert_instruction_before(ins
, *c
);
647 mir_remove_instruction(c
);
655 /* When we're 'squeezing down' the values in the IR, we maintain a hash
659 find_or_allocate_temp(compiler_context
*ctx
, unsigned hash
)
661 if ((hash
< 0) || (hash
>= SSA_FIXED_MINIMUM
))
664 unsigned temp
= (uintptr_t) _mesa_hash_table_u64_search(
665 ctx
->hash_to_temp
, hash
+ 1);
670 /* If no temp is find, allocate one */
671 temp
= ctx
->temp_count
++;
672 ctx
->max_hash
= MAX2(ctx
->max_hash
, hash
);
674 _mesa_hash_table_u64_insert(ctx
->hash_to_temp
,
675 hash
+ 1, (void *) ((uintptr_t) temp
+ 1));
680 /* Reassigns numbering to get rid of gaps in the indices */
683 mir_squeeze_index(compiler_context
*ctx
)
687 /* TODO don't leak old hash_to_temp */
688 ctx
->hash_to_temp
= _mesa_hash_table_u64_create(NULL
);
690 mir_foreach_instr_global(ctx
, ins
) {
691 if (ins
->compact_branch
) continue;
693 ins
->ssa_args
.dest
= find_or_allocate_temp(ctx
, ins
->ssa_args
.dest
);
694 ins
->ssa_args
.src0
= find_or_allocate_temp(ctx
, ins
->ssa_args
.src0
);
696 if (!ins
->ssa_args
.inline_constant
)
697 ins
->ssa_args
.src1
= find_or_allocate_temp(ctx
, ins
->ssa_args
.src1
);
702 static midgard_instruction
703 v_load_store_scratch(
709 /* We index by 32-bit vec4s */
710 unsigned byte
= (index
* 4 * 4);
712 midgard_instruction ins
= {
713 .type
= TAG_LOAD_STORE_4
,
721 .op
= is_store
? midgard_op_st_int4
: midgard_op_ld_int4
,
722 .swizzle
= SWIZZLE_XYZW
,
724 /* For register spilling - to thread local storage */
727 /* Splattered across, TODO combine logically */
728 .varying_parameters
= (byte
& 0x1FF) << 1,
729 .address
= (byte
>> 9)
734 /* r0 = r26, r1 = r27 */
735 assert(srcdest
== SSA_FIXED_REGISTER(26) || srcdest
== SSA_FIXED_REGISTER(27));
736 ins
.ssa_args
.src0
= (srcdest
== SSA_FIXED_REGISTER(27)) ? SSA_FIXED_REGISTER(1) : SSA_FIXED_REGISTER(0);
738 ins
.ssa_args
.dest
= srcdest
;
745 schedule_program(compiler_context
*ctx
)
747 struct ra_graph
*g
= NULL
;
748 bool spilled
= false;
749 int iter_count
= 1000; /* max iterations */
751 /* Number of 128-bit slots in memory we've spilled into */
752 unsigned spill_count
= 0;
754 midgard_promote_uniforms(ctx
, 8);
756 mir_foreach_block(ctx
, block
) {
757 midgard_pair_load_store(ctx
, block
);
760 /* Must be lowered right before RA */
761 mir_squeeze_index(ctx
);
762 mir_lower_special_reads(ctx
);
764 /* Lowering can introduce some dead moves */
766 mir_foreach_block(ctx
, block
) {
767 midgard_opt_dead_move_eliminate(ctx
, block
);
771 /* If we spill, find the best spill node and spill it */
773 unsigned spill_index
= ctx
->temp_count
;
775 /* All nodes are equal in spill cost, but we can't
776 * spill nodes written to from an unspill */
778 for (unsigned i
= 0; i
< ctx
->temp_count
; ++i
) {
779 ra_set_node_spill_cost(g
, i
, 1.0);
782 mir_foreach_instr_global(ctx
, ins
) {
783 if (ins
->type
!= TAG_LOAD_STORE_4
) continue;
784 if (ins
->load_store
.op
!= midgard_op_ld_int4
) continue;
785 if (ins
->load_store
.unknown
!= 0x1EEA) continue;
786 ra_set_node_spill_cost(g
, ins
->ssa_args
.dest
, -1.0);
789 int spill_node
= ra_get_best_spill_node(g
);
791 if (spill_node
< 0) {
792 mir_print_shader(ctx
);
796 /* Check the class. Work registers legitimately spill
797 * to TLS, but special registers just spill to work
799 unsigned class = ra_get_node_class(g
, spill_node
);
800 bool is_special
= (class >> 2) != REG_CLASS_WORK
;
801 bool is_special_w
= (class >> 2) == REG_CLASS_TEXW
;
803 /* Allocate TLS slot (maybe) */
804 unsigned spill_slot
= !is_special
? spill_count
++ : 0;
805 midgard_instruction
*spill_move
= NULL
;
807 /* For TLS, replace all stores to the spilled node. For
808 * special reads, just keep as-is; the class will be demoted
809 * implicitly. For special writes, spill to a work register */
811 if (!is_special
|| is_special_w
) {
812 mir_foreach_instr_global_safe(ctx
, ins
) {
813 if (ins
->compact_branch
) continue;
814 if (ins
->ssa_args
.dest
!= spill_node
) continue;
816 midgard_instruction st
;
819 spill_slot
= spill_index
++;
820 st
= v_mov(spill_node
, blank_alu_src
, spill_slot
);
822 ins
->ssa_args
.dest
= SSA_FIXED_REGISTER(26);
823 st
= v_load_store_scratch(ins
->ssa_args
.dest
, spill_slot
, true, ins
->mask
);
826 spill_move
= mir_insert_instruction_before(mir_next_op(ins
), st
);
833 /* Insert a load from TLS before the first consecutive
834 * use of the node, rewriting to use spilled indices to
835 * break up the live range. Or, for special, insert a
836 * move. Ironically the latter *increases* register
837 * pressure, but the two uses of the spilling mechanism
838 * are somewhat orthogonal. (special spilling is to use
839 * work registers to back special registers; TLS
840 * spilling is to use memory to back work registers) */
842 mir_foreach_block(ctx
, block
) {
844 bool consecutive_skip
= false;
845 unsigned consecutive_index
= 0;
847 mir_foreach_instr_in_block(block
, ins
) {
848 if (ins
->compact_branch
) continue;
850 /* We can't rewrite the move used to spill in the first place */
851 if (ins
== spill_move
) continue;
853 if (!mir_has_arg(ins
, spill_node
)) {
854 consecutive_skip
= false;
858 if (consecutive_skip
) {
860 mir_rewrite_index_src_single(ins
, spill_node
, consecutive_index
);
865 consecutive_index
= ++spill_index
;
867 midgard_instruction
*before
= ins
;
869 /* For a csel, go back one more not to break up the bundle */
870 if (ins
->type
== TAG_ALU_4
&& OP_IS_CSEL(ins
->alu
.op
))
871 before
= mir_prev_op(before
);
873 midgard_instruction st
;
877 st
= v_mov(spill_node
, blank_alu_src
, consecutive_index
);
880 st
= v_load_store_scratch(consecutive_index
, spill_slot
, false, 0xF);
883 mir_insert_instruction_before(before
, st
);
884 // consecutive_skip = true;
886 /* Special writes already have their move spilled in */
887 consecutive_index
= spill_slot
;
892 mir_rewrite_index_src_single(ins
, spill_node
, consecutive_index
);
900 mir_squeeze_index(ctx
);
903 g
= allocate_registers(ctx
, &spilled
);
904 } while(spilled
&& ((iter_count
--) > 0));
906 /* We can simplify a bit after RA */
908 mir_foreach_block(ctx
, block
) {
909 midgard_opt_post_move_eliminate(ctx
, block
, g
);
912 /* After RA finishes, we schedule all at once */
914 mir_foreach_block(ctx
, block
) {
915 schedule_block(ctx
, block
);
918 /* Finally, we create pipeline registers as a peephole pass after
919 * scheduling. This isn't totally optimal, since there are cases where
920 * the usage of pipeline registers can eliminate spills, but it does
923 mir_create_pipeline_registers(ctx
);
925 if (iter_count
<= 0) {
926 fprintf(stderr
, "panfrost: Gave up allocating registers, rendering will be incomplete\n");
930 /* Report spilling information. spill_count is in 128-bit slots (vec4 x
931 * fp32), but tls_size is in bytes, so multiply by 16 */
933 ctx
->tls_size
= spill_count
* 16;
935 install_registers(ctx
, g
);