2 * Copyright (C) 2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 #include "midgard_ops.h"
27 void mir_rewrite_index_src_single(midgard_instruction
*ins
, unsigned old
, unsigned new)
29 for (unsigned i
= 0; i
< ARRAY_SIZE(ins
->src
); ++i
) {
30 if (ins
->src
[i
] == old
)
35 void mir_rewrite_index_dst_single(midgard_instruction
*ins
, unsigned old
, unsigned new)
42 mir_get_swizzle(midgard_instruction
*ins
, unsigned idx
)
44 if (ins
->type
== TAG_ALU_4
) {
45 if (idx
== 2 || ins
->compact_branch
)
46 return ins
->cond_swizzle
;
48 unsigned b
= (idx
== 0) ? ins
->alu
.src1
: ins
->alu
.src2
;
50 midgard_vector_alu_src s
=
51 vector_alu_from_unsigned(b
);
54 } else if (ins
->type
== TAG_LOAD_STORE_4
) {
55 /* Main swizzle of a load is on the destination */
56 if (!OP_IS_STORE(ins
->load_store
.op
))
61 return ins
->load_store
.swizzle
;
65 (idx
== 2) ? ins
->load_store
.arg_2
: ins
->load_store
.arg_1
;
67 /* TODO: Integrate component count with properties */
68 unsigned components
= 1;
69 switch (ins
->load_store
.op
) {
70 case midgard_op_ld_int4
:
71 components
= (idx
== 0) ? 2 : 1;
73 case midgard_op_st_int4
:
74 components
= (idx
== 1) ? 2 : 1;
76 case midgard_op_ld_cubemap_coords
:
79 case midgard_op_ldst_perspective_division_z
:
82 case midgard_op_ldst_perspective_division_w
:
90 return component_to_swizzle(midgard_ldst_select(raw
).component
, components
);
93 unreachable("Unknown load/store source");
95 } else if (ins
->type
== TAG_TEXTURE_4
) {
98 return ins
->texture
.in_reg_swizzle
;
100 /* Swizzle on bias doesn't make sense */
103 unreachable("Unknown texture source");
106 unreachable("Unknown type");
111 mir_set_swizzle(midgard_instruction
*ins
, unsigned idx
, unsigned new)
113 if (ins
->type
== TAG_ALU_4
) {
114 if (idx
== 2 || ins
->compact_branch
) {
115 ins
->cond_swizzle
= new;
119 unsigned b
= (idx
== 0) ? ins
->alu
.src1
: ins
->alu
.src2
;
121 midgard_vector_alu_src s
=
122 vector_alu_from_unsigned(b
);
125 unsigned pack
= vector_alu_srco_unsigned(s
);
128 ins
->alu
.src1
= pack
;
130 ins
->alu
.src2
= pack
;
131 } else if (ins
->type
== TAG_LOAD_STORE_4
) {
132 /* Main swizzle of a load is on the destination */
133 if (!OP_IS_STORE(ins
->load_store
.op
))
138 ins
->load_store
.swizzle
= new;
143 (idx
== 2) ? ins
->load_store
.arg_2
: ins
->load_store
.arg_1
;
145 midgard_ldst_register_select sel
146 = midgard_ldst_select(raw
);
147 sel
.component
= swizzle_to_component(new);
148 uint8_t packed
= midgard_ldst_pack(sel
);
151 ins
->load_store
.arg_2
= packed
;
153 ins
->load_store
.arg_1
= packed
;
161 } else if (ins
->type
== TAG_TEXTURE_4
) {
164 ins
->texture
.in_reg_swizzle
= new;
171 unreachable("Unknown type");
176 mir_rewrite_index_src_single_swizzle(midgard_instruction
*ins
, unsigned old
, unsigned new, unsigned swizzle
)
178 for (unsigned i
= 0; i
< ARRAY_SIZE(ins
->src
); ++i
) {
179 if (ins
->src
[i
] != old
) continue;
183 mir_set_swizzle(ins
, i
,
184 pan_compose_swizzle(mir_get_swizzle(ins
, i
), swizzle
));
189 mir_rewrite_index_src(compiler_context
*ctx
, unsigned old
, unsigned new)
191 mir_foreach_instr_global(ctx
, ins
) {
192 mir_rewrite_index_src_single(ins
, old
, new);
197 mir_rewrite_index_src_swizzle(compiler_context
*ctx
, unsigned old
, unsigned new, unsigned swizzle
)
199 mir_foreach_instr_global(ctx
, ins
) {
200 mir_rewrite_index_src_single_swizzle(ins
, old
, new, swizzle
);
205 mir_rewrite_index_dst(compiler_context
*ctx
, unsigned old
, unsigned new)
207 mir_foreach_instr_global(ctx
, ins
) {
208 mir_rewrite_index_dst_single(ins
, old
, new);
213 mir_rewrite_index(compiler_context
*ctx
, unsigned old
, unsigned new)
215 mir_rewrite_index_src(ctx
, old
, new);
216 mir_rewrite_index_dst(ctx
, old
, new);
220 mir_use_count(compiler_context
*ctx
, unsigned value
)
222 unsigned used_count
= 0;
224 mir_foreach_instr_global(ctx
, ins
) {
225 if (mir_has_arg(ins
, value
))
232 /* Checks if a value is used only once (or totally dead), which is an important
233 * heuristic to figure out if certain optimizations are Worth It (TM) */
236 mir_single_use(compiler_context
*ctx
, unsigned value
)
238 /* We can replicate constants in places so who cares */
239 if (value
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
))
242 return mir_use_count(ctx
, value
) <= 1;
246 mir_nontrivial_raw_mod(midgard_vector_alu_src src
, bool is_int
)
249 return src
.mod
== midgard_int_shift
;
255 mir_nontrivial_mod(midgard_vector_alu_src src
, bool is_int
, unsigned mask
)
257 if (mir_nontrivial_raw_mod(src
, is_int
)) return true;
259 /* size-conversion */
260 if (src
.half
) return true;
263 for (unsigned c
= 0; c
< 4; ++c
) {
264 if (!(mask
& (1 << c
))) continue;
265 if (((src
.swizzle
>> (2*c
)) & 3) != c
) return true;
272 mir_nontrivial_source2_mod(midgard_instruction
*ins
)
274 bool is_int
= midgard_is_integer_op(ins
->alu
.op
);
276 midgard_vector_alu_src src2
=
277 vector_alu_from_unsigned(ins
->alu
.src2
);
279 return mir_nontrivial_mod(src2
, is_int
, ins
->mask
);
283 mir_nontrivial_source2_mod_simple(midgard_instruction
*ins
)
285 bool is_int
= midgard_is_integer_op(ins
->alu
.op
);
287 midgard_vector_alu_src src2
=
288 vector_alu_from_unsigned(ins
->alu
.src2
);
290 return mir_nontrivial_raw_mod(src2
, is_int
) || src2
.half
;
294 mir_nontrivial_outmod(midgard_instruction
*ins
)
296 bool is_int
= midgard_is_integer_op(ins
->alu
.op
);
297 unsigned mod
= ins
->alu
.outmod
;
303 /* Type conversion is a sort of outmod */
304 if (ins
->alu
.dest_override
!= midgard_dest_override_none
)
308 return mod
!= midgard_outmod_int_wrap
;
310 return mod
!= midgard_outmod_none
;
313 /* Checks if an index will be used as a special register -- basically, if we're
314 * used as the input to a non-ALU op */
317 mir_special_index(compiler_context
*ctx
, unsigned idx
)
319 mir_foreach_instr_global(ctx
, ins
) {
320 bool is_ldst
= ins
->type
== TAG_LOAD_STORE_4
;
321 bool is_tex
= ins
->type
== TAG_TEXTURE_4
;
322 bool is_writeout
= ins
->compact_branch
&& ins
->writeout
;
324 if (!(is_ldst
|| is_tex
|| is_writeout
))
327 if (mir_has_arg(ins
, idx
))
334 /* Is a node written before a given instruction? */
337 mir_is_written_before(compiler_context
*ctx
, midgard_instruction
*ins
, unsigned node
)
339 if (node
>= SSA_FIXED_MINIMUM
)
342 mir_foreach_instr_global(ctx
, q
) {
353 /* Creates a mask of the components of a node read by an instruction, by
354 * analyzing the swizzle with respect to the instruction's mask. E.g.:
356 * fadd r0.xz, r1.yyyy, r2.zwyx
358 * will return a mask of Z/Y for r2
362 mir_mask_of_read_components_single(unsigned swizzle
, unsigned outmask
)
366 for (unsigned c
= 0; c
< 4; ++c
) {
367 if (!(outmask
& (1 << c
))) continue;
369 unsigned comp
= (swizzle
>> (2*c
)) & 3;
377 mir_source_count(midgard_instruction
*ins
)
379 if (ins
->type
== TAG_ALU_4
) {
380 /* ALU is always binary, except csel */
381 return OP_IS_CSEL(ins
->alu
.op
) ? 3 : 2;
382 } else if (ins
->type
== TAG_LOAD_STORE_4
) {
383 bool load
= !OP_IS_STORE(ins
->load_store
.op
);
384 return (load
? 2 : 3);
385 } else if (ins
->type
== TAG_TEXTURE_4
) {
386 /* Coords, bias.. TODO: Offsets? */
389 unreachable("Invalid instruction type");
394 mir_mask_of_read_components(midgard_instruction
*ins
, unsigned node
)
398 for (unsigned i
= 0; i
< mir_source_count(ins
); ++i
) {
399 if (ins
->src
[i
] != node
) continue;
401 /* Branch writeout uses all components */
402 if (ins
->compact_branch
&& ins
->writeout
&& (i
== 0))
405 /* Conditional branches read one component (TODO: multi branch??) */
406 if (ins
->compact_branch
&& !ins
->prepacked_branch
&& ins
->branch
.conditional
&& (i
== 0))
409 /* ALU ops act componentwise so we need to pay attention to
410 * their mask. Texture/ldst does not so we don't clamp source
411 * readmasks based on the writemask */
412 unsigned qmask
= (ins
->type
== TAG_ALU_4
) ? ins
->mask
: 0xF;
414 /* Handle dot products and things */
415 if (ins
->type
== TAG_ALU_4
&& !ins
->compact_branch
) {
416 unsigned channel_override
=
417 GET_CHANNEL_COUNT(alu_opcode_props
[ins
->alu
.op
].props
);
419 if (channel_override
)
420 qmask
= mask_of(channel_override
);
423 unsigned swizzle
= mir_get_swizzle(ins
, i
);
424 unsigned m
= mir_mask_of_read_components_single(swizzle
, qmask
);
433 mir_ubo_shift(midgard_load_store_op op
)
436 case midgard_op_ld_ubo_char
:
438 case midgard_op_ld_ubo_char2
:
440 case midgard_op_ld_ubo_char4
:
442 case midgard_op_ld_ubo_short4
:
444 case midgard_op_ld_ubo_int4
:
447 unreachable("Invalid op");
451 /* Register allocation occurs after instruction scheduling, which is fine until
452 * we start needing to spill registers and therefore insert instructions into
453 * an already-scheduled program. We don't have to be terribly efficient about
454 * this, since spilling is already slow. So just semantically we need to insert
455 * the instruction into a new bundle before/after the bundle of the instruction
458 static midgard_bundle
459 mir_bundle_for_op(compiler_context
*ctx
, midgard_instruction ins
)
461 midgard_instruction
*u
= mir_upload_ins(ctx
, ins
);
463 midgard_bundle bundle
= {
465 .instruction_count
= 1,
466 .instructions
= { u
},
469 if (bundle
.tag
== TAG_ALU_4
) {
470 assert(OP_IS_MOVE(u
->alu
.op
));
473 size_t bytes_emitted
= sizeof(uint32_t) + sizeof(midgard_reg_info
) + sizeof(midgard_vector_alu
);
474 bundle
.padding
= ~(bytes_emitted
- 1) & 0xF;
475 bundle
.control
= ins
.type
| u
->unit
;
482 mir_bundle_idx_for_ins(midgard_instruction
*tag
, midgard_block
*block
)
484 midgard_bundle
*bundles
=
485 (midgard_bundle
*) block
->bundles
.data
;
487 size_t count
= (block
->bundles
.size
/ sizeof(midgard_bundle
));
489 for (unsigned i
= 0; i
< count
; ++i
) {
490 for (unsigned j
= 0; j
< bundles
[i
].instruction_count
; ++j
) {
491 if (bundles
[i
].instructions
[j
] == tag
)
496 mir_print_instruction(tag
);
497 unreachable("Instruction not scheduled in block");
501 mir_insert_instruction_before_scheduled(
502 compiler_context
*ctx
,
503 midgard_block
*block
,
504 midgard_instruction
*tag
,
505 midgard_instruction ins
)
507 unsigned before
= mir_bundle_idx_for_ins(tag
, block
);
508 size_t count
= util_dynarray_num_elements(&block
->bundles
, midgard_bundle
);
509 UNUSED
void *unused
= util_dynarray_grow(&block
->bundles
, midgard_bundle
, 1);
511 midgard_bundle
*bundles
= (midgard_bundle
*) block
->bundles
.data
;
512 memmove(bundles
+ before
+ 1, bundles
+ before
, (count
- before
) * sizeof(midgard_bundle
));
513 midgard_bundle
*before_bundle
= bundles
+ before
+ 1;
515 midgard_bundle
new = mir_bundle_for_op(ctx
, ins
);
516 memcpy(bundles
+ before
, &new, sizeof(new));
518 list_addtail(&new.instructions
[0]->link
, &before_bundle
->instructions
[0]->link
);
522 mir_insert_instruction_after_scheduled(
523 compiler_context
*ctx
,
524 midgard_block
*block
,
525 midgard_instruction
*tag
,
526 midgard_instruction ins
)
528 unsigned after
= mir_bundle_idx_for_ins(tag
, block
);
529 size_t count
= util_dynarray_num_elements(&block
->bundles
, midgard_bundle
);
530 UNUSED
void *unused
= util_dynarray_grow(&block
->bundles
, midgard_bundle
, 1);
532 midgard_bundle
*bundles
= (midgard_bundle
*) block
->bundles
.data
;
533 memmove(bundles
+ after
+ 2, bundles
+ after
+ 1, (count
- after
- 1) * sizeof(midgard_bundle
));
534 midgard_bundle
*after_bundle_1
= bundles
+ after
+ 2;
536 midgard_bundle
new = mir_bundle_for_op(ctx
, ins
);
537 memcpy(bundles
+ after
+ 1, &new, sizeof(new));
538 list_addtail(&new.instructions
[0]->link
, &after_bundle_1
->instructions
[0]->link
);
541 /* Flip the first-two arguments of a (binary) op. Currently ALU
542 * only, no known uses for ldst/tex */
545 mir_flip(midgard_instruction
*ins
)
547 unsigned temp
= ins
->src
[0];
548 ins
->src
[0] = ins
->src
[1];
551 assert(ins
->type
== TAG_ALU_4
);
553 temp
= ins
->alu
.src1
;
554 ins
->alu
.src1
= ins
->alu
.src2
;
555 ins
->alu
.src2
= temp
;
558 /* Before squashing, calculate ctx->temp_count just by observing the MIR */
561 mir_compute_temp_count(compiler_context
*ctx
)
566 unsigned max_dest
= 0;
568 mir_foreach_instr_global(ctx
, ins
) {
569 if (ins
->dest
< SSA_FIXED_MINIMUM
)
570 max_dest
= MAX2(max_dest
, ins
->dest
+ 1);
573 ctx
->temp_count
= max_dest
;