src/panfrost/midgard/mir.c

   1 /*
   2  * Copyright (C) 2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  */
  23
  24 #include "compiler.h"
  25 #include "midgard_ops.h"
  26
  27 void mir_rewrite_index_src_single(midgard_instruction *ins, unsigned old, unsigned new)
  28 {
  29         for (unsigned i = 0; i < ARRAY_SIZE(ins->src); ++i) {
  30                 if (ins->src[i] == old)
  31                         ins->src[i] = new;
  32         }
  33 }
  34
  35 void mir_rewrite_index_dst_single(midgard_instruction *ins, unsigned old, unsigned new)
  36 {
  37         if (ins->dest == old)
  38                 ins->dest = new;
  39 }
  40
  41 static midgard_vector_alu_src
  42 mir_get_alu_src(midgard_instruction *ins, unsigned idx)
  43 {
  44         unsigned b = (idx == 0) ? ins->alu.src1 : ins->alu.src2;
  45         return vector_alu_from_unsigned(b);
  46 }
  47
  48 unsigned
  49 mir_get_swizzle(midgard_instruction *ins, unsigned idx)
  50 {
  51         if (ins->type == TAG_ALU_4) {
  52                 if (idx == 2 || ins->compact_branch)
  53                         return ins->cond_swizzle;
  54
  55                 return (mir_get_alu_src(ins, idx)).swizzle;
  56         } else if (ins->type == TAG_LOAD_STORE_4) {
  57                 /* Main swizzle of a load is on the destination */
  58                 if (!OP_IS_STORE(ins->load_store.op))
  59                         idx++;
  60
  61                 switch (idx) {
  62                 case 0:
  63                         return ins->load_store.swizzle;
  64                 case 1:
  65                 case 2: {
  66                         uint8_t raw =
  67                                 (idx == 2) ? ins->load_store.arg_2 : ins->load_store.arg_1;
  68
  69                         /* TODO: Integrate component count with properties */
  70                         unsigned components = 1;
  71                         switch (ins->load_store.op) {
  72                         case midgard_op_ld_int4:
  73                                 components = (idx == 0) ? 2 : 1;
  74                                 break;
  75                         case midgard_op_st_int4:
  76                                 components = (idx == 1) ? 2 : 1;
  77                                 break;
  78                         case midgard_op_ld_cubemap_coords:
  79                                 components = 3;
  80                                 break;
  81                         case midgard_op_ldst_perspective_division_z:
  82                                 components = 3;
  83                                 break;
  84                         case midgard_op_ldst_perspective_division_w:
  85                                 components = 4;
  86                                 break;
  87                         default:
  88                                 components = 1;
  89                                 break;
  90                         }
  91
  92                         return component_to_swizzle(midgard_ldst_select(raw).component, components);
  93                 }
  94                 default:
  95                         unreachable("Unknown load/store source");
  96                 }
  97         } else if (ins->type == TAG_TEXTURE_4) {
  98                 switch (idx) {
  99                 case 0:
 100                         return ins->texture.in_reg_swizzle;
 101                 case 1:
 102                         /* Swizzle on bias doesn't make sense */
 103                         return 0;
 104                 default:
 105                         unreachable("Unknown texture source");
 106                 }
 107         } else {
 108                 unreachable("Unknown type");
 109         }
 110 }
 111
 112 void
 113 mir_set_swizzle(midgard_instruction *ins, unsigned idx, unsigned new)
 114 {
 115         if (ins->type == TAG_ALU_4) {
 116                 if (idx == 2 || ins->compact_branch) {
 117                         ins->cond_swizzle = new;
 118                         return;
 119                 }
 120
 121                 unsigned b = (idx == 0) ? ins->alu.src1 : ins->alu.src2;
 122
 123                 midgard_vector_alu_src s =
 124                         vector_alu_from_unsigned(b);
 125
 126                 s.swizzle = new;
 127                 unsigned pack = vector_alu_srco_unsigned(s);
 128
 129                 if (idx == 0)
 130                         ins->alu.src1 = pack;
 131                 else
 132                         ins->alu.src2 = pack;
 133         } else if (ins->type == TAG_LOAD_STORE_4) {
 134                 /* Main swizzle of a load is on the destination */
 135                 if (!OP_IS_STORE(ins->load_store.op))
 136                         idx++;
 137
 138                 switch (idx) {
 139                 case 0:
 140                         ins->load_store.swizzle = new;
 141                         break;
 142                 case 1:
 143                 case 2: {
 144                         uint8_t raw =
 145                                 (idx == 2) ? ins->load_store.arg_2 : ins->load_store.arg_1;
 146
 147                         midgard_ldst_register_select sel
 148                                 = midgard_ldst_select(raw);
 149                         sel.component = swizzle_to_component(new);
 150                         uint8_t packed = midgard_ldst_pack(sel);
 151
 152                         if (idx == 2)
 153                                 ins->load_store.arg_2 = packed;
 154                         else
 155                                 ins->load_store.arg_1 = packed;
 156
 157                         break;
 158                 }
 159                 default:
 160                         assert(new == 0);
 161                         break;
 162                 }
 163         } else if (ins->type == TAG_TEXTURE_4) {
 164                 switch (idx) {
 165                 case 0:
 166                         ins->texture.in_reg_swizzle = new;
 167                         break;
 168                 default:
 169                         assert(new == 0);
 170                         break;
 171                 }
 172         } else {
 173                 unreachable("Unknown type");
 174         }
 175 }
 176
 177 static void
 178 mir_rewrite_index_src_single_swizzle(midgard_instruction *ins, unsigned old, unsigned new, unsigned swizzle)
 179 {
 180         for (unsigned i = 0; i < ARRAY_SIZE(ins->src); ++i) {
 181                 if (ins->src[i] != old) continue;
 182
 183                 ins->src[i] = new;
 184
 185                 mir_set_swizzle(ins, i,
 186                         pan_compose_swizzle(mir_get_swizzle(ins, i), swizzle));
 187         }
 188 }
 189
 190 void
 191 mir_rewrite_index_src(compiler_context *ctx, unsigned old, unsigned new)
 192 {
 193         mir_foreach_instr_global(ctx, ins) {
 194                 mir_rewrite_index_src_single(ins, old, new);
 195         }
 196 }
 197
 198 void
 199 mir_rewrite_index_src_swizzle(compiler_context *ctx, unsigned old, unsigned new, unsigned swizzle)
 200 {
 201         mir_foreach_instr_global(ctx, ins) {
 202                 mir_rewrite_index_src_single_swizzle(ins, old, new, swizzle);
 203         }
 204 }
 205
 206 void
 207 mir_rewrite_index_dst(compiler_context *ctx, unsigned old, unsigned new)
 208 {
 209         mir_foreach_instr_global(ctx, ins) {
 210                 mir_rewrite_index_dst_single(ins, old, new);
 211         }
 212 }
 213
 214 void
 215 mir_rewrite_index(compiler_context *ctx, unsigned old, unsigned new)
 216 {
 217         mir_rewrite_index_src(ctx, old, new);
 218         mir_rewrite_index_dst(ctx, old, new);
 219 }
 220
 221 unsigned
 222 mir_use_count(compiler_context *ctx, unsigned value)
 223 {
 224         unsigned used_count = 0;
 225
 226         mir_foreach_instr_global(ctx, ins) {
 227                 if (mir_has_arg(ins, value))
 228                         ++used_count;
 229         }
 230
 231         return used_count;
 232 }
 233
 234 /* Checks if a value is used only once (or totally dead), which is an important
 235  * heuristic to figure out if certain optimizations are Worth It (TM) */
 236
 237 bool
 238 mir_single_use(compiler_context *ctx, unsigned value)
 239 {
 240         /* We can replicate constants in places so who cares */
 241         if (value == SSA_FIXED_REGISTER(REGISTER_CONSTANT))
 242                 return true;
 243
 244         return mir_use_count(ctx, value) <= 1;
 245 }
 246
 247 static bool
 248 mir_nontrivial_raw_mod(midgard_vector_alu_src src, bool is_int)
 249 {
 250         if (is_int)
 251                 return src.mod == midgard_int_shift;
 252         else
 253                 return src.mod;
 254 }
 255
 256 bool
 257 mir_nontrivial_mod(midgard_vector_alu_src src, bool is_int, unsigned mask)
 258 {
 259         if (mir_nontrivial_raw_mod(src, is_int)) return true;
 260
 261         /* size-conversion */
 262         if (src.half) return true;
 263
 264         /* swizzle */
 265         for (unsigned c = 0; c < 4; ++c) {
 266                 if (!(mask & (1 << c))) continue;
 267                 if (((src.swizzle >> (2*c)) & 3) != c) return true;
 268         }
 269
 270         return false;
 271 }
 272
 273 bool
 274 mir_nontrivial_source2_mod(midgard_instruction *ins)
 275 {
 276         bool is_int = midgard_is_integer_op(ins->alu.op);
 277
 278         midgard_vector_alu_src src2 =
 279                 vector_alu_from_unsigned(ins->alu.src2);
 280
 281         return mir_nontrivial_mod(src2, is_int, ins->mask);
 282 }
 283
 284 bool
 285 mir_nontrivial_source2_mod_simple(midgard_instruction *ins)
 286 {
 287         bool is_int = midgard_is_integer_op(ins->alu.op);
 288
 289         midgard_vector_alu_src src2 =
 290                 vector_alu_from_unsigned(ins->alu.src2);
 291
 292         return mir_nontrivial_raw_mod(src2, is_int) || src2.half;
 293 }
 294
 295 bool
 296 mir_nontrivial_outmod(midgard_instruction *ins)
 297 {
 298         bool is_int = midgard_is_integer_op(ins->alu.op);
 299         unsigned mod = ins->alu.outmod;
 300
 301         /* Pseudo-outmod */
 302         if (ins->invert)
 303                 return true;
 304
 305         /* Type conversion is a sort of outmod */
 306         if (ins->alu.dest_override != midgard_dest_override_none)
 307                 return true;
 308
 309         if (is_int)
 310                 return mod != midgard_outmod_int_wrap;
 311         else
 312                 return mod != midgard_outmod_none;
 313 }
 314
 315 /* Checks if an index will be used as a special register -- basically, if we're
 316  * used as the input to a non-ALU op */
 317
 318 bool
 319 mir_special_index(compiler_context *ctx, unsigned idx)
 320 {
 321         mir_foreach_instr_global(ctx, ins) {
 322                 bool is_ldst = ins->type == TAG_LOAD_STORE_4;
 323                 bool is_tex = ins->type == TAG_TEXTURE_4;
 324                 bool is_writeout = ins->compact_branch && ins->writeout;
 325
 326                 if (!(is_ldst || is_tex || is_writeout))
 327                         continue;
 328
 329                 if (mir_has_arg(ins, idx))
 330                         return true;
 331         }
 332
 333         return false;
 334 }
 335
 336 /* Is a node written before a given instruction? */
 337
 338 bool
 339 mir_is_written_before(compiler_context *ctx, midgard_instruction *ins, unsigned node)
 340 {
 341         if (node >= SSA_FIXED_MINIMUM)
 342                 return true;
 343
 344         mir_foreach_instr_global(ctx, q) {
 345                 if (q == ins)
 346                         break;
 347
 348                 if (q->dest == node)
 349                         return true;
 350         }
 351
 352         return false;
 353 }
 354
 355 /* Creates a mask of the components of a node read by an instruction, by
 356  * analyzing the swizzle with respect to the instruction's mask. E.g.:
 357  *
 358  *  fadd r0.xz, r1.yyyy, r2.zwyx
 359  *
 360  * will return a mask of Z/Y for r2
 361  */
 362
 363 static unsigned
 364 mir_mask_of_read_components_single(unsigned swizzle, unsigned outmask)
 365 {
 366         unsigned mask = 0;
 367
 368         for (unsigned c = 0; c < 4; ++c) {
 369                 if (!(outmask & (1 << c))) continue;
 370
 371                 unsigned comp = (swizzle >> (2*c)) & 3;
 372                 mask |= (1 << comp);
 373         }
 374
 375         return mask;
 376 }
 377
 378 static unsigned
 379 mir_source_count(midgard_instruction *ins)
 380 {
 381         if (ins->type == TAG_ALU_4) {
 382                 /* ALU is always binary, except csel */
 383                 return OP_IS_CSEL(ins->alu.op) ? 3 : 2;
 384         } else if (ins->type == TAG_LOAD_STORE_4) {
 385                 bool load = !OP_IS_STORE(ins->load_store.op);
 386                 return (load ? 2 : 3);
 387         } else if (ins->type == TAG_TEXTURE_4) {
 388                 /* Coords, bias.. TODO: Offsets? */
 389                 return 2;
 390         } else {
 391                 unreachable("Invalid instruction type");
 392         }
 393 }
 394
 395 unsigned
 396 mir_mask_of_read_components(midgard_instruction *ins, unsigned node)
 397 {
 398         unsigned mask = 0;
 399
 400         for (unsigned i = 0; i < mir_source_count(ins); ++i) {
 401                 if (ins->src[i] != node) continue;
 402
 403                 /* Branch writeout uses all components */
 404                 if (ins->compact_branch && ins->writeout && (i == 0))
 405                         return 0xF;
 406
 407                 /* Conditional branches read one component (TODO: multi branch??) */
 408                 if (ins->compact_branch && !ins->prepacked_branch && ins->branch.conditional && (i == 0))
 409                         return 0x1;
 410
 411                 /* ALU ops act componentwise so we need to pay attention to
 412                  * their mask. Texture/ldst does not so we don't clamp source
 413                  * readmasks based on the writemask */
 414                 unsigned qmask = (ins->type == TAG_ALU_4) ? ins->mask : 0xF;
 415
 416                 /* Handle dot products and things */
 417                 if (ins->type == TAG_ALU_4 && !ins->compact_branch) {
 418                         unsigned channel_override =
 419                                 GET_CHANNEL_COUNT(alu_opcode_props[ins->alu.op].props);
 420
 421                         if (channel_override)
 422                                 qmask = mask_of(channel_override);
 423                 }
 424
 425                 unsigned swizzle = mir_get_swizzle(ins, i);
 426                 unsigned m = mir_mask_of_read_components_single(swizzle, qmask);
 427
 428                mask |= m;
 429         }
 430
 431         return mask;
 432 }
 433
 434 unsigned
 435 mir_ubo_shift(midgard_load_store_op op)
 436 {
 437         switch (op) {
 438         case midgard_op_ld_ubo_char:
 439                 return 0;
 440         case midgard_op_ld_ubo_char2:
 441                 return 1;
 442         case midgard_op_ld_ubo_char4:
 443                 return 2;
 444         case midgard_op_ld_ubo_short4:
 445                 return 3;
 446         case midgard_op_ld_ubo_int4:
 447                 return 4;
 448         default:
 449                 unreachable("Invalid op");
 450         }
 451 }
 452
 453 /* Register allocation occurs after instruction scheduling, which is fine until
 454  * we start needing to spill registers and therefore insert instructions into
 455  * an already-scheduled program. We don't have to be terribly efficient about
 456  * this, since spilling is already slow. So just semantically we need to insert
 457  * the instruction into a new bundle before/after the bundle of the instruction
 458  * in question */
 459
 460 static midgard_bundle
 461 mir_bundle_for_op(compiler_context *ctx, midgard_instruction ins)
 462 {
 463         midgard_instruction *u = mir_upload_ins(ctx, ins);
 464
 465         midgard_bundle bundle = {
 466                 .tag = ins.type,
 467                 .instruction_count = 1,
 468                 .instructions = { u },
 469         };
 470
 471         if (bundle.tag == TAG_ALU_4) {
 472                 assert(OP_IS_MOVE(u->alu.op));
 473                 u->unit = UNIT_VMUL;
 474
 475                 size_t bytes_emitted = sizeof(uint32_t) + sizeof(midgard_reg_info) + sizeof(midgard_vector_alu);
 476                 bundle.padding = ~(bytes_emitted - 1) & 0xF;
 477                 bundle.control = ins.type | u->unit;
 478         }
 479
 480         return bundle;
 481 }
 482
 483 static unsigned
 484 mir_bundle_idx_for_ins(midgard_instruction *tag, midgard_block *block)
 485 {
 486         midgard_bundle *bundles =
 487                 (midgard_bundle *) block->bundles.data;
 488
 489         size_t count = (block->bundles.size / sizeof(midgard_bundle));
 490
 491         for (unsigned i = 0; i < count; ++i) {
 492                 for (unsigned j = 0; j < bundles[i].instruction_count; ++j) {
 493                         if (bundles[i].instructions[j] == tag)
 494                                 return i;
 495                 }
 496         }
 497
 498         mir_print_instruction(tag);
 499         unreachable("Instruction not scheduled in block");
 500 }
 501
 502 void
 503 mir_insert_instruction_before_scheduled(
 504         compiler_context *ctx,
 505         midgard_block *block,
 506         midgard_instruction *tag,
 507         midgard_instruction ins)
 508 {
 509         unsigned before = mir_bundle_idx_for_ins(tag, block);
 510         size_t count = util_dynarray_num_elements(&block->bundles, midgard_bundle);
 511         UNUSED void *unused = util_dynarray_grow(&block->bundles, midgard_bundle, 1);
 512
 513         midgard_bundle *bundles = (midgard_bundle *) block->bundles.data;
 514         memmove(bundles + before + 1, bundles + before, (count - before) * sizeof(midgard_bundle));
 515         midgard_bundle *before_bundle = bundles + before + 1;
 516
 517         midgard_bundle new = mir_bundle_for_op(ctx, ins);
 518         memcpy(bundles + before, &new, sizeof(new));
 519
 520         list_addtail(&new.instructions[0]->link, &before_bundle->instructions[0]->link);
 521 }
 522
 523 void
 524 mir_insert_instruction_after_scheduled(
 525         compiler_context *ctx,
 526         midgard_block *block,
 527         midgard_instruction *tag,
 528         midgard_instruction ins)
 529 {
 530         /* We need to grow the bundles array to add our new bundle */
 531         size_t count = util_dynarray_num_elements(&block->bundles, midgard_bundle);
 532         UNUSED void *unused = util_dynarray_grow(&block->bundles, midgard_bundle, 1);
 533
 534         /* Find the bundle that we want to insert after */
 535         unsigned after = mir_bundle_idx_for_ins(tag, block);
 536
 537         /* All the bundles after that one, we move ahead by one */
 538         midgard_bundle *bundles = (midgard_bundle *) block->bundles.data;
 539         memmove(bundles + after + 2, bundles + after + 1, (count - after - 1) * sizeof(midgard_bundle));
 540         midgard_bundle *after_bundle = bundles + after;
 541
 542         midgard_bundle new = mir_bundle_for_op(ctx, ins);
 543         memcpy(bundles + after + 1, &new, sizeof(new));
 544         list_add(&new.instructions[0]->link, &after_bundle->instructions[after_bundle->instruction_count - 1]->link);
 545 }
 546
 547 /* Flip the first-two arguments of a (binary) op. Currently ALU
 548  * only, no known uses for ldst/tex */
 549
 550 void
 551 mir_flip(midgard_instruction *ins)
 552 {
 553         unsigned temp = ins->src[0];
 554         ins->src[0] = ins->src[1];
 555         ins->src[1] = temp;
 556
 557         assert(ins->type == TAG_ALU_4);
 558
 559         temp = ins->alu.src1;
 560         ins->alu.src1 = ins->alu.src2;
 561         ins->alu.src2 = temp;
 562 }
 563
 564 /* Before squashing, calculate ctx->temp_count just by observing the MIR */
 565
 566 void
 567 mir_compute_temp_count(compiler_context *ctx)
 568 {
 569         if (ctx->temp_count)
 570                 return;
 571
 572         unsigned max_dest = 0;
 573
 574         mir_foreach_instr_global(ctx, ins) {
 575                 if (ins->dest < SSA_FIXED_MINIMUM)
 576                         max_dest = MAX2(max_dest, ins->dest + 1);
 577         }
 578
 579         ctx->temp_count = max_dest;
 580 }