2 * Copyright (C) 2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 #include "midgard_ops.h"
27 void mir_rewrite_index_src_single(midgard_instruction
*ins
, unsigned old
, unsigned new)
29 for (unsigned i
= 0; i
< ARRAY_SIZE(ins
->src
); ++i
) {
30 if (ins
->src
[i
] == old
)
35 void mir_rewrite_index_dst_single(midgard_instruction
*ins
, unsigned old
, unsigned new)
41 static midgard_vector_alu_src
42 mir_get_alu_src(midgard_instruction
*ins
, unsigned idx
)
44 unsigned b
= (idx
== 0) ? ins
->alu
.src1
: ins
->alu
.src2
;
45 return vector_alu_from_unsigned(b
);
49 mir_rewrite_index_src_single_swizzle(midgard_instruction
*ins
, unsigned old
, unsigned new, unsigned *swizzle
)
51 for (unsigned i
= 0; i
< ARRAY_SIZE(ins
->src
); ++i
) {
52 if (ins
->src
[i
] != old
) continue;
55 mir_compose_swizzle(ins
->swizzle
[i
], swizzle
, ins
->swizzle
[i
]);
60 mir_rewrite_index_src(compiler_context
*ctx
, unsigned old
, unsigned new)
62 mir_foreach_instr_global(ctx
, ins
) {
63 mir_rewrite_index_src_single(ins
, old
, new);
68 mir_rewrite_index_src_swizzle(compiler_context
*ctx
, unsigned old
, unsigned new, unsigned *swizzle
)
70 mir_foreach_instr_global(ctx
, ins
) {
71 mir_rewrite_index_src_single_swizzle(ins
, old
, new, swizzle
);
76 mir_rewrite_index_dst(compiler_context
*ctx
, unsigned old
, unsigned new)
78 mir_foreach_instr_global(ctx
, ins
) {
79 mir_rewrite_index_dst_single(ins
, old
, new);
84 mir_rewrite_index(compiler_context
*ctx
, unsigned old
, unsigned new)
86 mir_rewrite_index_src(ctx
, old
, new);
87 mir_rewrite_index_dst(ctx
, old
, new);
91 mir_use_count(compiler_context
*ctx
, unsigned value
)
93 unsigned used_count
= 0;
95 mir_foreach_instr_global(ctx
, ins
) {
96 if (mir_has_arg(ins
, value
))
103 /* Checks if a value is used only once (or totally dead), which is an important
104 * heuristic to figure out if certain optimizations are Worth It (TM) */
107 mir_single_use(compiler_context
*ctx
, unsigned value
)
109 /* We can replicate constants in places so who cares */
110 if (value
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
))
113 return mir_use_count(ctx
, value
) <= 1;
117 mir_nontrivial_raw_mod(midgard_vector_alu_src src
, bool is_int
)
120 return src
.mod
== midgard_int_shift
;
126 mir_nontrivial_mod(midgard_vector_alu_src src
, bool is_int
, unsigned mask
, unsigned *swizzle
)
128 if (mir_nontrivial_raw_mod(src
, is_int
)) return true;
130 /* size-conversion */
131 if (src
.half
) return true;
133 for (unsigned c
= 0; c
< 16; ++c
) {
134 if (!(mask
& (1 << c
))) continue;
135 if (swizzle
[c
] != c
) return true;
142 mir_nontrivial_source2_mod(midgard_instruction
*ins
)
144 bool is_int
= midgard_is_integer_op(ins
->alu
.op
);
146 midgard_vector_alu_src src2
=
147 vector_alu_from_unsigned(ins
->alu
.src2
);
149 return mir_nontrivial_mod(src2
, is_int
, ins
->mask
, ins
->swizzle
[1]);
153 mir_nontrivial_source2_mod_simple(midgard_instruction
*ins
)
155 bool is_int
= midgard_is_integer_op(ins
->alu
.op
);
157 midgard_vector_alu_src src2
=
158 vector_alu_from_unsigned(ins
->alu
.src2
);
160 return mir_nontrivial_raw_mod(src2
, is_int
) || src2
.half
;
164 mir_nontrivial_outmod(midgard_instruction
*ins
)
166 bool is_int
= midgard_is_integer_op(ins
->alu
.op
);
167 unsigned mod
= ins
->alu
.outmod
;
173 /* Type conversion is a sort of outmod */
174 if (ins
->alu
.dest_override
!= midgard_dest_override_none
)
178 return mod
!= midgard_outmod_int_wrap
;
180 return mod
!= midgard_outmod_none
;
183 /* Checks if an index will be used as a special register -- basically, if we're
184 * used as the input to a non-ALU op */
187 mir_special_index(compiler_context
*ctx
, unsigned idx
)
189 mir_foreach_instr_global(ctx
, ins
) {
190 bool is_ldst
= ins
->type
== TAG_LOAD_STORE_4
;
191 bool is_tex
= ins
->type
== TAG_TEXTURE_4
;
192 bool is_writeout
= ins
->compact_branch
&& ins
->writeout
;
194 if (!(is_ldst
|| is_tex
|| is_writeout
))
197 if (mir_has_arg(ins
, idx
))
204 /* Is a node written before a given instruction? */
207 mir_is_written_before(compiler_context
*ctx
, midgard_instruction
*ins
, unsigned node
)
209 if (node
>= SSA_FIXED_MINIMUM
)
212 mir_foreach_instr_global(ctx
, q
) {
223 /* Grabs the type size. */
226 mir_typesize(midgard_instruction
*ins
)
228 if (ins
->compact_branch
)
229 return midgard_reg_mode_32
;
231 /* TODO: Type sizes for texture */
232 if (ins
->type
== TAG_TEXTURE_4
)
233 return midgard_reg_mode_32
;
235 if (ins
->type
== TAG_LOAD_STORE_4
)
236 return GET_LDST_SIZE(load_store_opcode_props
[ins
->load_store
.op
].props
);
238 if (ins
->type
== TAG_ALU_4
) {
239 midgard_reg_mode mode
= ins
->alu
.reg_mode
;
241 /* If we have an override, step down by half */
242 if (ins
->alu
.dest_override
!= midgard_dest_override_none
) {
243 assert(mode
> midgard_reg_mode_8
);
250 unreachable("Invalid instruction type");
253 /* Grabs the size of a source */
256 mir_srcsize(midgard_instruction
*ins
, unsigned i
)
258 if (ins
->type
== TAG_LOAD_STORE_4
) {
259 if (OP_HAS_ADDRESS(ins
->load_store
.op
)) {
261 return midgard_reg_mode_64
;
263 bool zext
= ins
->load_store
.arg_1
& 0x80;
264 return zext
? midgard_reg_mode_32
: midgard_reg_mode_64
;
269 /* TODO: 16-bit textures/ldst */
270 if (ins
->type
== TAG_TEXTURE_4
|| ins
->type
== TAG_LOAD_STORE_4
)
271 return midgard_reg_mode_32
;
273 /* TODO: 16-bit branches */
274 if (ins
->compact_branch
)
275 return midgard_reg_mode_32
;
278 /* TODO: 16-bit conditions, ffma */
279 return midgard_reg_mode_32
;
282 /* Default to type of the instruction */
284 midgard_reg_mode mode
= ins
->alu
.reg_mode
;
286 /* If we have a half modifier, step down by half */
288 if ((mir_get_alu_src(ins
, i
)).half
) {
289 assert(mode
> midgard_reg_mode_8
);
297 mir_mode_for_destsize(unsigned size
)
301 return midgard_reg_mode_8
;
303 return midgard_reg_mode_16
;
305 return midgard_reg_mode_32
;
307 return midgard_reg_mode_64
;
309 unreachable("Unknown destination size");
313 /* ...and the inverse */
316 mir_bytes_for_mode(midgard_reg_mode mode
)
319 case midgard_reg_mode_8
:
321 case midgard_reg_mode_16
:
323 case midgard_reg_mode_32
:
325 case midgard_reg_mode_64
:
328 unreachable("Invalid register mode");
333 mir_from_bytemask(uint16_t bytemask
, midgard_reg_mode mode
)
336 unsigned count
= mir_bytes_for_mode(mode
);
338 for (unsigned c
= 0, d
= 0; c
< 16; c
+= count
, ++d
) {
339 bool a
= (bytemask
& (1 << c
)) != 0;
341 for (unsigned q
= c
; q
< count
; ++q
)
342 assert(((bytemask
& (1 << q
)) != 0) == a
);
350 /* Rounds up a bytemask to fill a given component count. Iterate each
351 * component, and check if any bytes in the component are masked on */
354 mir_round_bytemask_up(uint16_t mask
, midgard_reg_mode mode
)
356 unsigned bytes
= mir_bytes_for_mode(mode
);
357 unsigned maxmask
= mask_of(bytes
);
358 unsigned channels
= 16 / bytes
;
360 for (unsigned c
= 0; c
< channels
; ++c
) {
361 unsigned submask
= maxmask
<< (c
* bytes
);
370 /* Grabs the per-byte mask of an instruction (as opposed to per-component) */
373 mir_bytemask(midgard_instruction
*ins
)
375 return pan_to_bytemask(mir_bytes_for_mode(mir_typesize(ins
)) * 8, ins
->mask
);
379 mir_set_bytemask(midgard_instruction
*ins
, uint16_t bytemask
)
381 ins
->mask
= mir_from_bytemask(bytemask
, mir_typesize(ins
));
384 /* Checks if we should use an upper destination override, rather than the lower
385 * one in the IR. Returns zero if no, returns the bytes to shift otherwise */
388 mir_upper_override(midgard_instruction
*ins
)
390 /* If there is no override, there is no upper override, tautology */
391 if (ins
->alu
.dest_override
== midgard_dest_override_none
)
394 /* Make sure we didn't already lower somehow */
395 assert(ins
->alu
.dest_override
== midgard_dest_override_lower
);
397 /* What is the mask in terms of currently? */
398 midgard_reg_mode type
= mir_typesize(ins
);
400 /* There are 16 bytes per vector, so there are (16/bytes)
401 * components per vector. So the magic half is half of
402 * (16/bytes), which simplifies to 8/bytes */
404 unsigned threshold
= 8 / mir_bytes_for_mode(type
);
406 /* How many components did we shift over? */
407 unsigned zeroes
= __builtin_ctz(ins
->mask
);
409 /* Did we hit the threshold? */
410 return (zeroes
>= threshold
) ? threshold
: 0;
413 /* Creates a mask of the components of a node read by an instruction, by
414 * analyzing the swizzle with respect to the instruction's mask. E.g.:
416 * fadd r0.xz, r1.yyyy, r2.zwyx
418 * will return a mask of Z/Y for r2
422 mir_bytemask_of_read_components_single(unsigned *swizzle
, unsigned inmask
, midgard_reg_mode mode
)
426 for (unsigned c
= 0; c
< MIR_VEC_COMPONENTS
; ++c
) {
427 if (!(inmask
& (1 << c
))) continue;
428 cmask
|= (1 << swizzle
[c
]);
431 return pan_to_bytemask(mir_bytes_for_mode(mode
) * 8, cmask
);
435 mir_bytemask_of_read_components_index(midgard_instruction
*ins
, unsigned i
)
437 if (ins
->compact_branch
&& ins
->writeout
&& (i
== 0)) {
438 /* Non-ZS writeout uses all components */
439 if (!ins
->writeout_depth
&& !ins
->writeout_stencil
)
442 /* For ZS-writeout, if both Z and S are written we need two
443 * components, otherwise we only need one.
445 if (ins
->writeout_depth
&& ins
->writeout_stencil
)
451 /* Conditional branches read one 32-bit component = 4 bytes (TODO: multi branch??) */
452 if (ins
->compact_branch
&& ins
->branch
.conditional
&& (i
== 0))
455 /* ALU ops act componentwise so we need to pay attention to
456 * their mask. Texture/ldst does not so we don't clamp source
457 * readmasks based on the writemask */
458 unsigned qmask
= (ins
->type
== TAG_ALU_4
) ? ins
->mask
: ~0;
460 /* Handle dot products and things */
461 if (ins
->type
== TAG_ALU_4
&& !ins
->compact_branch
) {
462 unsigned props
= alu_opcode_props
[ins
->alu
.op
].props
;
464 unsigned channel_override
= GET_CHANNEL_COUNT(props
);
466 if (channel_override
)
467 qmask
= mask_of(channel_override
);
470 return mir_bytemask_of_read_components_single(ins
->swizzle
[i
], qmask
, mir_srcsize(ins
, i
));
474 mir_bytemask_of_read_components(midgard_instruction
*ins
, unsigned node
)
481 mir_foreach_src(ins
, i
) {
482 if (ins
->src
[i
] != node
) continue;
483 mask
|= mir_bytemask_of_read_components_index(ins
, i
);
489 /* Register allocation occurs after instruction scheduling, which is fine until
490 * we start needing to spill registers and therefore insert instructions into
491 * an already-scheduled program. We don't have to be terribly efficient about
492 * this, since spilling is already slow. So just semantically we need to insert
493 * the instruction into a new bundle before/after the bundle of the instruction
496 static midgard_bundle
497 mir_bundle_for_op(compiler_context
*ctx
, midgard_instruction ins
)
499 midgard_instruction
*u
= mir_upload_ins(ctx
, ins
);
501 midgard_bundle bundle
= {
503 .instruction_count
= 1,
504 .instructions
= { u
},
507 if (bundle
.tag
== TAG_ALU_4
) {
508 assert(OP_IS_MOVE(u
->alu
.op
));
511 size_t bytes_emitted
= sizeof(uint32_t) + sizeof(midgard_reg_info
) + sizeof(midgard_vector_alu
);
512 bundle
.padding
= ~(bytes_emitted
- 1) & 0xF;
513 bundle
.control
= ins
.type
| u
->unit
;
520 mir_bundle_idx_for_ins(midgard_instruction
*tag
, midgard_block
*block
)
522 midgard_bundle
*bundles
=
523 (midgard_bundle
*) block
->bundles
.data
;
525 size_t count
= (block
->bundles
.size
/ sizeof(midgard_bundle
));
527 for (unsigned i
= 0; i
< count
; ++i
) {
528 for (unsigned j
= 0; j
< bundles
[i
].instruction_count
; ++j
) {
529 if (bundles
[i
].instructions
[j
] == tag
)
534 mir_print_instruction(tag
);
535 unreachable("Instruction not scheduled in block");
539 mir_insert_instruction_before_scheduled(
540 compiler_context
*ctx
,
541 midgard_block
*block
,
542 midgard_instruction
*tag
,
543 midgard_instruction ins
)
545 unsigned before
= mir_bundle_idx_for_ins(tag
, block
);
546 size_t count
= util_dynarray_num_elements(&block
->bundles
, midgard_bundle
);
547 UNUSED
void *unused
= util_dynarray_grow(&block
->bundles
, midgard_bundle
, 1);
549 midgard_bundle
*bundles
= (midgard_bundle
*) block
->bundles
.data
;
550 memmove(bundles
+ before
+ 1, bundles
+ before
, (count
- before
) * sizeof(midgard_bundle
));
551 midgard_bundle
*before_bundle
= bundles
+ before
+ 1;
553 midgard_bundle
new = mir_bundle_for_op(ctx
, ins
);
554 memcpy(bundles
+ before
, &new, sizeof(new));
556 list_addtail(&new.instructions
[0]->link
, &before_bundle
->instructions
[0]->link
);
557 block
->quadword_count
+= midgard_tag_props
[new.tag
].size
;
561 mir_insert_instruction_after_scheduled(
562 compiler_context
*ctx
,
563 midgard_block
*block
,
564 midgard_instruction
*tag
,
565 midgard_instruction ins
)
567 /* We need to grow the bundles array to add our new bundle */
568 size_t count
= util_dynarray_num_elements(&block
->bundles
, midgard_bundle
);
569 UNUSED
void *unused
= util_dynarray_grow(&block
->bundles
, midgard_bundle
, 1);
571 /* Find the bundle that we want to insert after */
572 unsigned after
= mir_bundle_idx_for_ins(tag
, block
);
574 /* All the bundles after that one, we move ahead by one */
575 midgard_bundle
*bundles
= (midgard_bundle
*) block
->bundles
.data
;
576 memmove(bundles
+ after
+ 2, bundles
+ after
+ 1, (count
- after
- 1) * sizeof(midgard_bundle
));
577 midgard_bundle
*after_bundle
= bundles
+ after
;
579 midgard_bundle
new = mir_bundle_for_op(ctx
, ins
);
580 memcpy(bundles
+ after
+ 1, &new, sizeof(new));
581 list_add(&new.instructions
[0]->link
, &after_bundle
->instructions
[after_bundle
->instruction_count
- 1]->link
);
582 block
->quadword_count
+= midgard_tag_props
[new.tag
].size
;
585 /* Flip the first-two arguments of a (binary) op. Currently ALU
586 * only, no known uses for ldst/tex */
589 mir_flip(midgard_instruction
*ins
)
591 unsigned temp
= ins
->src
[0];
592 ins
->src
[0] = ins
->src
[1];
595 assert(ins
->type
== TAG_ALU_4
);
597 temp
= ins
->alu
.src1
;
598 ins
->alu
.src1
= ins
->alu
.src2
;
599 ins
->alu
.src2
= temp
;
601 unsigned temp_swizzle
[16];
602 memcpy(temp_swizzle
, ins
->swizzle
[0], sizeof(ins
->swizzle
[0]));
603 memcpy(ins
->swizzle
[0], ins
->swizzle
[1], sizeof(ins
->swizzle
[0]));
604 memcpy(ins
->swizzle
[1], temp_swizzle
, sizeof(ins
->swizzle
[0]));
607 /* Before squashing, calculate ctx->temp_count just by observing the MIR */
610 mir_compute_temp_count(compiler_context
*ctx
)
615 unsigned max_dest
= 0;
617 mir_foreach_instr_global(ctx
, ins
) {
618 if (ins
->dest
< SSA_FIXED_MINIMUM
)
619 max_dest
= MAX2(max_dest
, ins
->dest
+ 1);
622 ctx
->temp_count
= max_dest
;