src/panfrost/midgard/mir.c

   1 /*
   2  * Copyright (C) 2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  */
  23
  24 #include "compiler.h"
  25 #include "midgard_ops.h"
  26
  27 void mir_rewrite_index_src_single(midgard_instruction *ins, unsigned old, unsigned new)
  28 {
  29         for (unsigned i = 0; i < ARRAY_SIZE(ins->src); ++i) {
  30                 if (ins->src[i] == old)
  31                         ins->src[i] = new;
  32         }
  33 }
  34
  35 void mir_rewrite_index_dst_single(midgard_instruction *ins, unsigned old, unsigned new)
  36 {
  37         if (ins->dest == old)
  38                 ins->dest = new;
  39 }
  40
  41 unsigned
  42 mir_get_swizzle(midgard_instruction *ins, unsigned idx)
  43 {
  44         if (ins->type == TAG_ALU_4) {
  45                 if (idx == 2)
  46                         return ins->csel_swizzle;
  47
  48                 unsigned b = (idx == 0) ? ins->alu.src1 : ins->alu.src2;
  49
  50                 midgard_vector_alu_src s =
  51                         vector_alu_from_unsigned(b);
  52
  53                 return s.swizzle;
  54         } else if (ins->type == TAG_LOAD_STORE_4) {
  55                 /* Main swizzle of a load is on the destination */
  56                 if (!OP_IS_STORE(ins->load_store.op))
  57                         idx++;
  58
  59                 switch (idx) {
  60                 case 0:
  61                         return ins->load_store.swizzle;
  62                 case 1:
  63                 case 2: {
  64                         uint8_t raw =
  65                                 (idx == 2) ? ins->load_store.arg_2 : ins->load_store.arg_1;
  66
  67                         return component_to_swizzle(midgard_ldst_select(raw).component);
  68                 }
  69                 default:
  70                         unreachable("Unknown load/store source");
  71                 }
  72         } else if (ins->type == TAG_TEXTURE_4) {
  73                 switch (idx) {
  74                 case 0:
  75                         return ins->texture.in_reg_swizzle;
  76                 case 1:
  77                         /* Swizzle on bias doesn't make sense */
  78                         return 0;
  79                 default:
  80                         unreachable("Unknown texture source");
  81                 }
  82         } else {
  83                 unreachable("Unknown type");
  84         }
  85 }
  86
  87 void
  88 mir_set_swizzle(midgard_instruction *ins, unsigned idx, unsigned new)
  89 {
  90         if (ins->type == TAG_ALU_4) {
  91                 unsigned b = (idx == 0) ? ins->alu.src1 : ins->alu.src2;
  92
  93                 midgard_vector_alu_src s =
  94                         vector_alu_from_unsigned(b);
  95
  96                 s.swizzle = new;
  97                 unsigned pack = vector_alu_srco_unsigned(s);
  98
  99                 if (idx == 0)
 100                         ins->alu.src1 = pack;
 101                 else
 102                         ins->alu.src2 = pack;
 103         } else if (ins->type == TAG_LOAD_STORE_4) {
 104                 /* Main swizzle of a load is on the destination */
 105                 if (!OP_IS_STORE(ins->load_store.op))
 106                         idx++;
 107
 108                 switch (idx) {
 109                 case 0:
 110                         ins->load_store.swizzle = new;
 111                         break;
 112                 case 1:
 113                 case 2: {
 114                         uint8_t raw =
 115                                 (idx == 2) ? ins->load_store.arg_2 : ins->load_store.arg_1;
 116
 117                         midgard_ldst_register_select sel
 118                                 = midgard_ldst_select(raw);
 119                         sel.component = swizzle_to_component(new);
 120                         uint8_t packed = midgard_ldst_pack(sel);
 121
 122                         if (idx == 2)
 123                                 ins->load_store.arg_2 = packed;
 124                         else
 125                                 ins->load_store.arg_1 = packed;
 126
 127                         break;
 128                 }
 129                 default:
 130                         assert(new == 0);
 131                         break;
 132                 }
 133         } else if (ins->type == TAG_TEXTURE_4) {
 134                 switch (idx) {
 135                 case 0:
 136                         ins->texture.in_reg_swizzle = new;
 137                         break;
 138                 default:
 139                         assert(new == 0);
 140                         break;
 141                 }
 142         } else {
 143                 unreachable("Unknown type");
 144         }
 145 }
 146
 147 static void
 148 mir_rewrite_index_src_single_swizzle(midgard_instruction *ins, unsigned old, unsigned new, unsigned swizzle)
 149 {
 150         for (unsigned i = 0; i < ARRAY_SIZE(ins->src); ++i) {
 151                 if (ins->src[i] != old) continue;
 152
 153                 ins->src[i] = new;
 154
 155                 mir_set_swizzle(ins, i,
 156                         pan_compose_swizzle(mir_get_swizzle(ins, i), swizzle));
 157         }
 158 }
 159
 160 void
 161 mir_rewrite_index_src(compiler_context *ctx, unsigned old, unsigned new)
 162 {
 163         mir_foreach_instr_global(ctx, ins) {
 164                 mir_rewrite_index_src_single(ins, old, new);
 165         }
 166 }
 167
 168 void
 169 mir_rewrite_index_src_swizzle(compiler_context *ctx, unsigned old, unsigned new, unsigned swizzle)
 170 {
 171         mir_foreach_instr_global(ctx, ins) {
 172                 mir_rewrite_index_src_single_swizzle(ins, old, new, swizzle);
 173         }
 174 }
 175
 176 void
 177 mir_rewrite_index_dst(compiler_context *ctx, unsigned old, unsigned new)
 178 {
 179         mir_foreach_instr_global(ctx, ins) {
 180                 mir_rewrite_index_dst_single(ins, old, new);
 181         }
 182 }
 183
 184 void
 185 mir_rewrite_index(compiler_context *ctx, unsigned old, unsigned new)
 186 {
 187         mir_rewrite_index_src(ctx, old, new);
 188         mir_rewrite_index_dst(ctx, old, new);
 189 }
 190
 191 unsigned
 192 mir_use_count(compiler_context *ctx, unsigned value)
 193 {
 194         unsigned used_count = 0;
 195
 196         mir_foreach_instr_global(ctx, ins) {
 197                 if (mir_has_arg(ins, value))
 198                         ++used_count;
 199         }
 200
 201         return used_count;
 202 }
 203
 204 /* Checks if a value is used only once (or totally dead), which is an important
 205  * heuristic to figure out if certain optimizations are Worth It (TM) */
 206
 207 bool
 208 mir_single_use(compiler_context *ctx, unsigned value)
 209 {
 210         /* We can replicate constants in places so who cares */
 211         if (value == SSA_FIXED_REGISTER(REGISTER_CONSTANT))
 212                 return true;
 213
 214         return mir_use_count(ctx, value) <= 1;
 215 }
 216
 217 static bool
 218 mir_nontrivial_raw_mod(midgard_vector_alu_src src, bool is_int)
 219 {
 220         if (is_int)
 221                 return src.mod == midgard_int_shift;
 222         else
 223                 return src.mod;
 224 }
 225
 226 bool
 227 mir_nontrivial_mod(midgard_vector_alu_src src, bool is_int, unsigned mask)
 228 {
 229         if (mir_nontrivial_raw_mod(src, is_int)) return true;
 230
 231         /* size-conversion */
 232         if (src.half) return true;
 233
 234         /* swizzle */
 235         for (unsigned c = 0; c < 4; ++c) {
 236                 if (!(mask & (1 << c))) continue;
 237                 if (((src.swizzle >> (2*c)) & 3) != c) return true;
 238         }
 239
 240         return false;
 241 }
 242
 243 bool
 244 mir_nontrivial_source2_mod(midgard_instruction *ins)
 245 {
 246         bool is_int = midgard_is_integer_op(ins->alu.op);
 247
 248         midgard_vector_alu_src src2 =
 249                 vector_alu_from_unsigned(ins->alu.src2);
 250
 251         return mir_nontrivial_mod(src2, is_int, ins->mask);
 252 }
 253
 254 bool
 255 mir_nontrivial_source2_mod_simple(midgard_instruction *ins)
 256 {
 257         bool is_int = midgard_is_integer_op(ins->alu.op);
 258
 259         midgard_vector_alu_src src2 =
 260                 vector_alu_from_unsigned(ins->alu.src2);
 261
 262         return mir_nontrivial_raw_mod(src2, is_int) || src2.half;
 263 }
 264
 265 bool
 266 mir_nontrivial_outmod(midgard_instruction *ins)
 267 {
 268         bool is_int = midgard_is_integer_op(ins->alu.op);
 269         unsigned mod = ins->alu.outmod;
 270
 271         /* Pseudo-outmod */
 272         if (ins->invert)
 273                 return true;
 274
 275         /* Type conversion is a sort of outmod */
 276         if (ins->alu.dest_override != midgard_dest_override_none)
 277                 return true;
 278
 279         if (is_int)
 280                 return mod != midgard_outmod_int_wrap;
 281         else
 282                 return mod != midgard_outmod_none;
 283 }
 284
 285 /* Checks if an index will be used as a special register -- basically, if we're
 286  * used as the input to a non-ALU op */
 287
 288 bool
 289 mir_special_index(compiler_context *ctx, unsigned idx)
 290 {
 291         mir_foreach_instr_global(ctx, ins) {
 292                 bool is_ldst = ins->type == TAG_LOAD_STORE_4;
 293                 bool is_tex = ins->type == TAG_TEXTURE_4;
 294                 bool is_writeout = ins->compact_branch && ins->writeout;
 295
 296                 if (!(is_ldst || is_tex || is_writeout))
 297                         continue;
 298
 299                 if (mir_has_arg(ins, idx))
 300                         return true;
 301         }
 302
 303         return false;
 304 }
 305
 306 /* Is a node written before a given instruction? */
 307
 308 bool
 309 mir_is_written_before(compiler_context *ctx, midgard_instruction *ins, unsigned node)
 310 {
 311         if (node >= SSA_FIXED_MINIMUM)
 312                 return true;
 313
 314         mir_foreach_instr_global(ctx, q) {
 315                 if (q == ins)
 316                         break;
 317
 318                 if (q->dest == node)
 319                         return true;
 320         }
 321
 322         return false;
 323 }
 324
 325 /* Creates a mask of the components of a node read by an instruction, by
 326  * analyzing the swizzle with respect to the instruction's mask. E.g.:
 327  *
 328  *  fadd r0.xz, r1.yyyy, r2.zwyx
 329  *
 330  * will return a mask of Z/Y for r2
 331  */
 332
 333 static unsigned
 334 mir_mask_of_read_components_single(unsigned swizzle, unsigned outmask)
 335 {
 336         unsigned mask = 0;
 337
 338         for (unsigned c = 0; c < 4; ++c) {
 339                 if (!(outmask & (1 << c))) continue;
 340
 341                 unsigned comp = (swizzle >> (2*c)) & 3;
 342                 mask |= (1 << comp);
 343         }
 344
 345         return mask;
 346 }
 347
 348 static unsigned
 349 mir_source_count(midgard_instruction *ins)
 350 {
 351         if (ins->type == TAG_ALU_4) {
 352                 /* ALU is always binary, except csel */
 353                 return OP_IS_CSEL(ins->alu.op) ? 3 : 2;
 354         } else if (ins->type == TAG_LOAD_STORE_4) {
 355                 bool load = !OP_IS_STORE(ins->load_store.op);
 356                 return (load ? 2 : 3);
 357         } else if (ins->type == TAG_TEXTURE_4) {
 358                 /* Coords, bias.. TODO: Offsets? */
 359                 return 2;
 360         } else {
 361                 unreachable("Invalid instruction type");
 362         }
 363 }
 364
 365 static unsigned
 366 mir_component_count_implicit(midgard_instruction *ins, unsigned i)
 367 {
 368         if (ins->type == TAG_LOAD_STORE_4) {
 369                 switch (ins->load_store.op) {
 370                         /* Address implicitly 64-bit */
 371                 case midgard_op_ld_int4:
 372                         return (i == 0) ? 1 : 0;
 373
 374                 case midgard_op_st_int4:
 375                         return (i == 1) ? 1 : 0;
 376
 377                 default:
 378                         return 0;
 379                 }
 380         }
 381
 382         return 0;
 383 }
 384
 385 unsigned
 386 mir_mask_of_read_components(midgard_instruction *ins, unsigned node)
 387 {
 388         unsigned mask = 0;
 389
 390         for (unsigned i = 0; i < mir_source_count(ins); ++i) {
 391                 if (ins->src[i] != node) continue;
 392
 393                 /* Branch writeout uses all components */
 394                 if (ins->compact_branch && ins->writeout && (i == 0))
 395                         return 0xF;
 396
 397                 unsigned swizzle = mir_get_swizzle(ins, i);
 398                 unsigned m = mir_mask_of_read_components_single(swizzle, ins->mask);
 399
 400                 /* Sometimes multi-arg ops are passed implicitly */
 401                 unsigned implicit = mir_component_count_implicit(ins, i);
 402                 assert(implicit < 2);
 403
 404                 /* Extend the mask */
 405                 if (implicit == 1) {
 406                         /* Ensure it's a single bit currently */
 407                         assert((m >> __builtin_ctz(m)) == 0x1);
 408
 409                         /* Set the next bit to extend one*/
 410                         m |= (m << 1);
 411                 }
 412
 413                 /* Handle dot products and things */
 414                 if (ins->type == TAG_ALU_4 && !ins->compact_branch) {
 415                         unsigned channel_override =
 416                                 GET_CHANNEL_COUNT(alu_opcode_props[ins->alu.op].props);
 417
 418                         if (channel_override)
 419                                 m = mask_of(channel_override);
 420                 }
 421
 422                 mask |= m;
 423         }
 424
 425         return mask;
 426 }
 427
 428 unsigned
 429 mir_ubo_shift(midgard_load_store_op op)
 430 {
 431         switch (op) {
 432         case midgard_op_ld_ubo_char:
 433                 return 0;
 434         case midgard_op_ld_ubo_char2:
 435                 return 1;
 436         case midgard_op_ld_ubo_char4:
 437                 return 2;
 438         case midgard_op_ld_ubo_short4:
 439                 return 3;
 440         case midgard_op_ld_ubo_int4:
 441                 return 4;
 442         default:
 443                 unreachable("Invalid op");
 444         }
 445 }
 446
 447 /* Register allocation occurs after instruction scheduling, which is fine until
 448  * we start needing to spill registers and therefore insert instructions into
 449  * an already-scheduled program. We don't have to be terribly efficient about
 450  * this, since spilling is already slow. So just semantically we need to insert
 451  * the instruction into a new bundle before/after the bundle of the instruction
 452  * in question */
 453
 454 static midgard_bundle
 455 mir_bundle_for_op(compiler_context *ctx, midgard_instruction ins)
 456 {
 457         midgard_instruction *u = mir_upload_ins(ctx, ins);
 458
 459         midgard_bundle bundle = {
 460                 .tag = ins.type,
 461                 .instruction_count = 1,
 462                 .instructions = { u },
 463         };
 464
 465         if (bundle.tag == TAG_ALU_4) {
 466                 assert(OP_IS_MOVE(u->alu.op));
 467                 u->unit = UNIT_VMUL;
 468
 469                 size_t bytes_emitted = sizeof(uint32_t) + sizeof(midgard_reg_info) + sizeof(midgard_vector_alu);
 470                 bundle.padding = ~(bytes_emitted - 1) & 0xF;
 471                 bundle.control = ins.type | u->unit;
 472         }
 473
 474         return bundle;
 475 }
 476
 477 static unsigned
 478 mir_bundle_idx_for_ins(midgard_instruction *tag, midgard_block *block)
 479 {
 480         midgard_bundle *bundles =
 481                 (midgard_bundle *) block->bundles.data;
 482
 483         size_t count = (block->bundles.size / sizeof(midgard_bundle));
 484
 485         for (unsigned i = 0; i < count; ++i) {
 486                 for (unsigned j = 0; j < bundles[i].instruction_count; ++j) {
 487                         if (bundles[i].instructions[j] == tag)
 488                                 return i;
 489                 }
 490         }
 491
 492         mir_print_instruction(tag);
 493         unreachable("Instruction not scheduled in block");
 494 }
 495
 496 void
 497 mir_insert_instruction_before_scheduled(
 498         compiler_context *ctx,
 499         midgard_block *block,
 500         midgard_instruction *tag,
 501         midgard_instruction ins)
 502 {
 503         unsigned before = mir_bundle_idx_for_ins(tag, block);
 504         size_t count = util_dynarray_num_elements(&block->bundles, midgard_bundle);
 505         UNUSED void *unused = util_dynarray_grow(&block->bundles, midgard_bundle, 1);
 506
 507         midgard_bundle *bundles = (midgard_bundle *) block->bundles.data;
 508         memmove(bundles + before + 1, bundles + before, (count - before) * sizeof(midgard_bundle));
 509         midgard_bundle *before_bundle = bundles + before + 1;
 510
 511         midgard_bundle new = mir_bundle_for_op(ctx, ins);
 512         memcpy(bundles + before, &new, sizeof(new));
 513
 514         list_addtail(&new.instructions[0]->link, &before_bundle->instructions[0]->link);
 515 }
 516
 517 void
 518 mir_insert_instruction_after_scheduled(
 519         compiler_context *ctx,
 520         midgard_block *block,
 521         midgard_instruction *tag,
 522         midgard_instruction ins)
 523 {
 524         unsigned after = mir_bundle_idx_for_ins(tag, block);
 525         size_t count = util_dynarray_num_elements(&block->bundles, midgard_bundle);
 526         UNUSED void *unused = util_dynarray_grow(&block->bundles, midgard_bundle, 1);
 527
 528         midgard_bundle *bundles = (midgard_bundle *) block->bundles.data;
 529         memmove(bundles + after + 2, bundles + after + 1, (count - after - 1) * sizeof(midgard_bundle));
 530         midgard_bundle *after_bundle_1 = bundles + after + 2;
 531
 532         midgard_bundle new = mir_bundle_for_op(ctx, ins);
 533         memcpy(bundles + after + 1, &new, sizeof(new));
 534         list_addtail(&new.instructions[0]->link, &after_bundle_1->instructions[0]->link);
 535 }