2 * Copyright (C) 2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 #include "midgard_ops.h"
27 void mir_rewrite_index_src_single(midgard_instruction
*ins
, unsigned old
, unsigned new)
29 for (unsigned i
= 0; i
< ARRAY_SIZE(ins
->src
); ++i
) {
30 if (ins
->src
[i
] == old
)
35 void mir_rewrite_index_dst_single(midgard_instruction
*ins
, unsigned old
, unsigned new)
42 mir_get_swizzle(midgard_instruction
*ins
, unsigned idx
)
44 if (ins
->type
== TAG_ALU_4
) {
46 return ins
->csel_swizzle
;
48 unsigned b
= (idx
== 0) ? ins
->alu
.src1
: ins
->alu
.src2
;
50 midgard_vector_alu_src s
=
51 vector_alu_from_unsigned(b
);
54 } else if (ins
->type
== TAG_LOAD_STORE_4
) {
55 /* Main swizzle of a load is on the destination */
56 if (!OP_IS_STORE(ins
->load_store
.op
))
61 return ins
->load_store
.swizzle
;
65 (idx
== 2) ? ins
->load_store
.arg_2
: ins
->load_store
.arg_1
;
67 return component_to_swizzle(midgard_ldst_select(raw
).component
);
70 unreachable("Unknown load/store source");
72 } else if (ins
->type
== TAG_TEXTURE_4
) {
75 return ins
->texture
.in_reg_swizzle
;
77 /* Swizzle on bias doesn't make sense */
80 unreachable("Unknown texture source");
83 unreachable("Unknown type");
88 mir_set_swizzle(midgard_instruction
*ins
, unsigned idx
, unsigned new)
90 if (ins
->type
== TAG_ALU_4
) {
91 unsigned b
= (idx
== 0) ? ins
->alu
.src1
: ins
->alu
.src2
;
93 midgard_vector_alu_src s
=
94 vector_alu_from_unsigned(b
);
97 unsigned pack
= vector_alu_srco_unsigned(s
);
100 ins
->alu
.src1
= pack
;
102 ins
->alu
.src2
= pack
;
103 } else if (ins
->type
== TAG_LOAD_STORE_4
) {
104 /* Main swizzle of a load is on the destination */
105 if (!OP_IS_STORE(ins
->load_store
.op
))
110 ins
->load_store
.swizzle
= new;
115 (idx
== 2) ? ins
->load_store
.arg_2
: ins
->load_store
.arg_1
;
117 midgard_ldst_register_select sel
118 = midgard_ldst_select(raw
);
119 sel
.component
= swizzle_to_component(new);
120 uint8_t packed
= midgard_ldst_pack(sel
);
123 ins
->load_store
.arg_2
= packed
;
125 ins
->load_store
.arg_1
= packed
;
133 } else if (ins
->type
== TAG_TEXTURE_4
) {
136 ins
->texture
.in_reg_swizzle
= new;
143 unreachable("Unknown type");
148 mir_rewrite_index_src_single_swizzle(midgard_instruction
*ins
, unsigned old
, unsigned new, unsigned swizzle
)
150 for (unsigned i
= 0; i
< ARRAY_SIZE(ins
->src
); ++i
) {
151 if (ins
->src
[i
] != old
) continue;
155 mir_set_swizzle(ins
, i
,
156 pan_compose_swizzle(mir_get_swizzle(ins
, i
), swizzle
));
161 mir_rewrite_index_src(compiler_context
*ctx
, unsigned old
, unsigned new)
163 mir_foreach_instr_global(ctx
, ins
) {
164 mir_rewrite_index_src_single(ins
, old
, new);
169 mir_rewrite_index_src_swizzle(compiler_context
*ctx
, unsigned old
, unsigned new, unsigned swizzle
)
171 mir_foreach_instr_global(ctx
, ins
) {
172 mir_rewrite_index_src_single_swizzle(ins
, old
, new, swizzle
);
177 mir_rewrite_index_src_tag(compiler_context
*ctx
, unsigned old
, unsigned new, unsigned tag
)
179 mir_foreach_instr_global(ctx
, ins
) {
180 if (ins
->type
!= tag
)
183 mir_rewrite_index_src_single(ins
, old
, new);
190 mir_rewrite_index_dst(compiler_context
*ctx
, unsigned old
, unsigned new)
192 mir_foreach_instr_global(ctx
, ins
) {
193 mir_rewrite_index_dst_single(ins
, old
, new);
198 mir_rewrite_index_dst_tag(compiler_context
*ctx
, unsigned old
, unsigned new, unsigned tag
)
200 mir_foreach_instr_global(ctx
, ins
) {
201 if (ins
->type
!= tag
)
204 if (ins
->dest
== old
)
212 mir_rewrite_index(compiler_context
*ctx
, unsigned old
, unsigned new)
214 mir_rewrite_index_src(ctx
, old
, new);
215 mir_rewrite_index_dst(ctx
, old
, new);
219 mir_use_count(compiler_context
*ctx
, unsigned value
)
221 unsigned used_count
= 0;
223 mir_foreach_instr_global(ctx
, ins
) {
224 if (mir_has_arg(ins
, value
))
231 /* Checks if a value is used only once (or totally dead), which is an important
232 * heuristic to figure out if certain optimizations are Worth It (TM) */
235 mir_single_use(compiler_context
*ctx
, unsigned value
)
237 /* We can replicate constants in places so who cares */
238 if (value
== SSA_FIXED_REGISTER(REGISTER_CONSTANT
))
241 return mir_use_count(ctx
, value
) <= 1;
245 mir_nontrivial_raw_mod(midgard_vector_alu_src src
, bool is_int
)
248 return src
.mod
== midgard_int_shift
;
254 mir_nontrivial_mod(midgard_vector_alu_src src
, bool is_int
, unsigned mask
)
256 if (mir_nontrivial_raw_mod(src
, is_int
)) return true;
258 /* size-conversion */
259 if (src
.half
) return true;
262 for (unsigned c
= 0; c
< 4; ++c
) {
263 if (!(mask
& (1 << c
))) continue;
264 if (((src
.swizzle
>> (2*c
)) & 3) != c
) return true;
271 mir_nontrivial_source2_mod(midgard_instruction
*ins
)
273 bool is_int
= midgard_is_integer_op(ins
->alu
.op
);
275 midgard_vector_alu_src src2
=
276 vector_alu_from_unsigned(ins
->alu
.src2
);
278 return mir_nontrivial_mod(src2
, is_int
, ins
->mask
);
282 mir_nontrivial_source2_mod_simple(midgard_instruction
*ins
)
284 bool is_int
= midgard_is_integer_op(ins
->alu
.op
);
286 midgard_vector_alu_src src2
=
287 vector_alu_from_unsigned(ins
->alu
.src2
);
289 return mir_nontrivial_raw_mod(src2
, is_int
) || src2
.half
;
293 mir_nontrivial_outmod(midgard_instruction
*ins
)
295 bool is_int
= midgard_is_integer_op(ins
->alu
.op
);
296 unsigned mod
= ins
->alu
.outmod
;
302 /* Type conversion is a sort of outmod */
303 if (ins
->alu
.dest_override
!= midgard_dest_override_none
)
307 return mod
!= midgard_outmod_int_wrap
;
309 return mod
!= midgard_outmod_none
;
312 /* Checks if an index will be used as a special register -- basically, if we're
313 * used as the input to a non-ALU op */
316 mir_special_index(compiler_context
*ctx
, unsigned idx
)
318 mir_foreach_instr_global(ctx
, ins
) {
319 bool is_ldst
= ins
->type
== TAG_LOAD_STORE_4
;
320 bool is_tex
= ins
->type
== TAG_TEXTURE_4
;
322 if (!(is_ldst
|| is_tex
))
325 if (mir_has_arg(ins
, idx
))
332 /* Is a node written before a given instruction? */
335 mir_is_written_before(compiler_context
*ctx
, midgard_instruction
*ins
, unsigned node
)
337 if (node
>= SSA_FIXED_MINIMUM
)
340 mir_foreach_instr_global(ctx
, q
) {
351 /* Creates a mask of the components of a node read by an instruction, by
352 * analyzing the swizzle with respect to the instruction's mask. E.g.:
354 * fadd r0.xz, r1.yyyy, r2.zwyx
356 * will return a mask of Z/Y for r2
360 mir_mask_of_read_components_single(unsigned swizzle
, unsigned outmask
)
364 for (unsigned c
= 0; c
< 4; ++c
) {
365 if (!(outmask
& (1 << c
))) continue;
367 unsigned comp
= (swizzle
>> (2*c
)) & 3;
375 mir_source_count(midgard_instruction
*ins
)
377 if (ins
->type
== TAG_ALU_4
) {
378 /* ALU is always binary */
380 } else if (ins
->type
== TAG_LOAD_STORE_4
) {
381 bool load
= !OP_IS_STORE(ins
->load_store
.op
);
382 return (load
? 2 : 3);
383 } else if (ins
->type
== TAG_TEXTURE_4
) {
384 /* Coords, bias.. TODO: Offsets? */
387 unreachable("Invalid instruction type");
392 mir_component_count_implicit(midgard_instruction
*ins
, unsigned i
)
394 if (ins
->type
== TAG_LOAD_STORE_4
) {
395 switch (ins
->load_store
.op
) {
396 /* Address implicitly 64-bit */
397 case midgard_op_ld_int4
:
398 return (i
== 0) ? 1 : 0;
400 case midgard_op_st_int4
:
401 return (i
== 1) ? 1 : 0;
412 mir_mask_of_read_components(midgard_instruction
*ins
, unsigned node
)
416 for (unsigned i
= 0; i
< mir_source_count(ins
); ++i
) {
417 if (ins
->src
[i
] != node
) continue;
419 unsigned swizzle
= mir_get_swizzle(ins
, i
);
420 unsigned m
= mir_mask_of_read_components_single(swizzle
, ins
->mask
);
422 /* Sometimes multi-arg ops are passed implicitly */
423 unsigned implicit
= mir_component_count_implicit(ins
, i
);
424 assert(implicit
< 2);
426 /* Extend the mask */
428 /* Ensure it's a single bit currently */
429 assert((m
>> __builtin_ctz(m
)) == 0x1);
431 /* Set the next bit to extend one*/
442 mir_ubo_shift(midgard_load_store_op op
)
445 case midgard_op_ld_ubo_char
:
447 case midgard_op_ld_ubo_char2
:
449 case midgard_op_ld_ubo_char4
:
451 case midgard_op_ld_ubo_short4
:
453 case midgard_op_ld_ubo_int4
:
456 unreachable("Invalid op");
460 /* Register allocation occurs after instruction scheduling, which is fine until
461 * we start needing to spill registers and therefore insert instructions into
462 * an already-scheduled program. We don't have to be terribly efficient about
463 * this, since spilling is already slow. So just semantically we need to insert
464 * the instruction into a new bundle before/after the bundle of the instruction
467 static midgard_bundle
468 mir_bundle_for_op(compiler_context
*ctx
, midgard_instruction ins
)
470 midgard_instruction
*u
= mir_upload_ins(ctx
, ins
);
472 midgard_bundle bundle
= {
474 .instruction_count
= 1,
475 .instructions
= { u
},
478 if (bundle
.tag
== TAG_ALU_4
) {
479 assert(OP_IS_MOVE(u
->alu
.op
));
482 size_t bytes_emitted
= sizeof(uint32_t) + sizeof(midgard_reg_info
) + sizeof(midgard_vector_alu
);
483 bundle
.padding
= ~(bytes_emitted
- 1) & 0xF;
484 bundle
.control
= ins
.type
| u
->unit
;
491 mir_bundle_idx_for_ins(midgard_instruction
*tag
, midgard_block
*block
)
493 midgard_bundle
*bundles
=
494 (midgard_bundle
*) block
->bundles
.data
;
496 size_t count
= (block
->bundles
.size
/ sizeof(midgard_bundle
));
498 for (unsigned i
= 0; i
< count
; ++i
) {
499 for (unsigned j
= 0; j
< bundles
[i
].instruction_count
; ++j
) {
500 if (bundles
[i
].instructions
[j
] == tag
)
505 mir_print_instruction(tag
);
506 unreachable("Instruction not scheduled in block");
510 mir_insert_instruction_before_scheduled(
511 compiler_context
*ctx
,
512 midgard_block
*block
,
513 midgard_instruction
*tag
,
514 midgard_instruction ins
)
516 unsigned before
= mir_bundle_idx_for_ins(tag
, block
);
517 size_t count
= util_dynarray_num_elements(&block
->bundles
, midgard_bundle
);
518 UNUSED
void *unused
= util_dynarray_grow(&block
->bundles
, midgard_bundle
, 1);
520 midgard_bundle
*bundles
= (midgard_bundle
*) block
->bundles
.data
;
521 memmove(bundles
+ before
+ 1, bundles
+ before
, (count
- before
) * sizeof(midgard_bundle
));
522 midgard_bundle
*before_bundle
= bundles
+ before
+ 1;
524 midgard_bundle
new = mir_bundle_for_op(ctx
, ins
);
525 memcpy(bundles
+ before
, &new, sizeof(new));
527 list_addtail(&new.instructions
[0]->link
, &before_bundle
->instructions
[0]->link
);
531 mir_insert_instruction_after_scheduled(
532 compiler_context
*ctx
,
533 midgard_block
*block
,
534 midgard_instruction
*tag
,
535 midgard_instruction ins
)
537 unsigned after
= mir_bundle_idx_for_ins(tag
, block
);
538 size_t count
= util_dynarray_num_elements(&block
->bundles
, midgard_bundle
);
539 UNUSED
void *unused
= util_dynarray_grow(&block
->bundles
, midgard_bundle
, 1);
541 midgard_bundle
*bundles
= (midgard_bundle
*) block
->bundles
.data
;
542 memmove(bundles
+ after
+ 2, bundles
+ after
+ 1, (count
- after
- 1) * sizeof(midgard_bundle
));
543 midgard_bundle
*after_bundle_1
= bundles
+ after
+ 2;
545 midgard_bundle
new = mir_bundle_for_op(ctx
, ins
);
546 memcpy(bundles
+ after
+ 1, &new, sizeof(new));
547 list_addtail(&new.instructions
[0]->link
, &after_bundle_1
->instructions
[0]->link
);