2 * Copyright (C) 2019 Collabora, Ltd.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * Authors (Collabora):
24 * Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
29 /* This pass promotes reads from uniforms from load/store ops to uniform
30 * registers if it is beneficial to do so. Normally, this saves both
31 * instructions and total register pressure, but it does take a toll on the
32 * number of work registers that are available, so this is a balance.
34 * To cope, we take as an argument the maximum work register pressure in the
35 * program so we allow that many registers through at minimum, to prevent
36 * spilling. If we spill anyway, I mean, it's a lose-lose at that point. */
39 midgard_promote_uniforms(compiler_context
*ctx
, unsigned register_pressure
)
41 /* For our purposes, pressure is capped at the number of vec4 work
42 * registers, not live values which would consider spills */
43 register_pressure
= MAX2(register_pressure
, 16);
45 mir_foreach_instr_global_safe(ctx
, ins
) {
46 if (ins
->type
!= TAG_LOAD_STORE_4
) continue;
47 if (!OP_IS_UBO_READ(ins
->load_store
.op
)) continue;
49 unsigned lo
= ins
->load_store
.varying_parameters
>> 7;
50 unsigned hi
= ins
->load_store
.address
;
52 /* TODO: Combine fields logically */
53 unsigned address
= (hi
<< 3) | lo
;
55 /* Check this is UBO 0 */
56 if (ins
->load_store
.unknown
& 0xF) continue;
58 /* Check we're accessing directly */
59 if (ins
->load_store
.unknown
!= 0x1E00) continue;
61 /* Check if it's a promotable range */
62 unsigned uniform_reg
= 23 - address
;
64 if (address
> 16) continue;
65 if (register_pressure
> uniform_reg
) continue;
67 /* It is, great! Let's promote */
69 ctx
->uniform_cutoff
= MAX2(ctx
->uniform_cutoff
, address
+ 1);
70 unsigned promoted
= SSA_FIXED_REGISTER(uniform_reg
);
72 /* We do need the move for safety for a non-SSA dest, or if
73 * we're being fed into a special class */
75 bool needs_move
= ins
->ssa_args
.dest
>= ctx
->func
->impl
->ssa_alloc
;
76 needs_move
|= mir_special_index(ctx
, ins
->ssa_args
.dest
);
79 midgard_instruction mov
= v_mov(promoted
, blank_alu_src
, ins
->ssa_args
.dest
);
80 mir_insert_instruction_before(ins
, mov
);
82 mir_rewrite_index_src(ctx
, ins
->ssa_args
.dest
, promoted
);
85 mir_remove_instruction(ins
);