src/panfrost/midgard/mir_promote_uniforms.c

   1 /*
   2  * Copyright (C) 2019 Collabora, Ltd.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors (Collabora):
  24  *   Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
  25  */
  26
  27 #include "compiler.h"
  28 #include "util/u_math.h"
  29
  30 /* This pass promotes reads from uniforms from load/store ops to uniform
  31  * registers if it is beneficial to do so. Normally, this saves both
  32  * instructions and total register pressure, but it does take a toll on the
  33  * number of work registers that are available, so this is a balance.
  34  *
  35  * To cope, we take as an argument the maximum work register pressure in the
  36  * program so we allow that many registers through at minimum, to prevent
  37  * spilling. If we spill anyway, I mean, it's a lose-lose at that point. */
  38
  39 void
  40 midgard_promote_uniforms(compiler_context *ctx, unsigned promoted_count)
  41 {
  42         mir_foreach_instr_global_safe(ctx, ins) {
  43                 if (ins->type != TAG_LOAD_STORE_4) continue;
  44                 if (!OP_IS_UBO_READ(ins->load_store.op)) continue;
  45
  46                 /* TODO: promote unaligned access via swizzle? */
  47                 unsigned off = ins->constants[0];
  48                 if (off & 0xF) continue;
  49
  50                 unsigned address = off / 16;
  51
  52                 /* Check this is UBO 0 */
  53                 if (ins->load_store.arg_1) continue;
  54
  55                 /* Check we're accessing directly */
  56                 if (ins->load_store.arg_2 != 0x1E) continue;
  57
  58                 /* Check if it's a promotable range */
  59                 unsigned uniform_reg = 23 - address;
  60
  61                 if (address >= promoted_count) continue;
  62
  63                 /* It is, great! Let's promote */
  64
  65                 ctx->uniform_cutoff = MAX2(ctx->uniform_cutoff, address + 1);
  66                 unsigned promoted = SSA_FIXED_REGISTER(uniform_reg);
  67
  68                 /* We do need the move for safety for a non-SSA dest, or if
  69                  * we're being fed into a special class */
  70
  71                 bool needs_move = ins->dest & IS_REG;
  72                 needs_move |= mir_special_index(ctx, ins->dest);
  73
  74                 if (needs_move) {
  75                         midgard_instruction mov = v_mov(promoted, ins->dest);
  76
  77                         if (ins->load_64)
  78                                 mov.alu.reg_mode = midgard_reg_mode_64;
  79
  80                         mir_set_bytemask(&mov, mir_bytemask(ins));
  81                         mir_insert_instruction_before(ctx, ins, mov);
  82                 } else {
  83                         mir_rewrite_index_src(ctx, ins->dest, promoted);
  84                 }
  85
  86                 mir_remove_instruction(ins);
  87         }
  88 }