2 Copyright (c) 2013, IIT Madras
5 Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
7 * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
8 * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
9 * Neither the name of IIT Madras nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
11 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
12 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
16 /*=== library imports === */
19 import AXI4_Lite_Types::*;
21 /*======================== */
22 /*==== Project imports ====*/
23 import defined_types::*;
24 `include "instance_defines.bsv"
25 /*=========================*/
28 method Bit#(1) msip_int;
29 method Bit#(1) mtip_int;
30 method Bit#(`Reg_width) mtime;
31 interface AXI4_Lite_Slave_IFC#(`PADDR, `Reg_width,`USERSPACE) axi4_slave;
34 function Reg#(t) writeSideEffect(Reg#(t) r, Action a);
35 return (interface Reg;
36 method t _read = r._read;
37 method Action _write(t x);
45 module mkclint(Ifc_clint);
47 AXI4_Lite_Slave_Xactor_IFC #(`PADDR, `Reg_width, `USERSPACE) s_xactor <- mkAXI4_Lite_Slave_Xactor;
48 Wire#(Bool) wr_mtimecmp_written<-mkDWire(False);
49 Reg#(Bit#(1)) msip <-mkReg(0);
50 Reg#(Bit#(1)) mtip <-mkReg(0);
51 Reg#(Bit#(64)) rgmtime<-mkReg(0);
52 Reg#(Bit#(64)) rgmtimecmp<-mkReg(0);
53 Reg#(Bit#(64)) csr_mtimecmp=writeSideEffect(rgmtimecmp,wr_mtimecmp_written._write(True));
54 Reg#(Bit#(2)) rg_tick <-mkReg(0);
56 rule generate_time_interrupt(!wr_mtimecmp_written);
57 mtip<=pack(rgmtime>=rgmtimecmp);
59 rule clear_interrupt(wr_mtimecmp_written);
70 rule axi_read_transaction;
71 let ar <- pop_o(s_xactor.o_rd_addr);
72 let r = AXI4_Lite_Rd_Data {rresp: AXI4_LITE_OKAY, rdata: ?, ruser: 0};
73 case (ar.araddr[15:0]) matches
74 'h0000: r.rdata=zeroExtend(msip); // MSIP interrupt bit
75 'h4000: r.rdata=csr_mtimecmp;
76 'hbff8: r.rdata=rgmtime;
77 default: begin r.rdata=0; r.rresp=AXI4_LITE_SLVERR; end
79 s_xactor.i_rd_data.enq(r);
82 rule axi_write_transaction;
83 let aw <- pop_o(s_xactor.o_wr_addr);
84 let w <- pop_o(s_xactor.o_wr_data);
85 let r = AXI4_Lite_Wr_Resp {bresp: AXI4_LITE_OKAY, buser: 0 };
87 case (aw.awaddr[15:0]) matches
88 'h0000: msip<=w.wdata[0]; // MSIP interrupt bit
89 'h4000: csr_mtimecmp<=w.wdata;
90 default: r.bresp=AXI4_LITE_SLVERR;
92 s_xactor.i_wr_resp.enq (r);
95 interface axi4_slave = s_xactor.axi_side;
96 method Bit#(1) msip_int=msip;
97 method Bit#(1) mtip_int=mtip;
98 method Bit#(`Reg_width) mtime = rgmtime;