1 // Copyright (c) 2017 Bluespec, Inc. All Rights Reserved
5 // ================================================================
6 // See export list below
7 // ================================================================
12 // RTL-level interfaces (signals/buses)
13 FlexBus_Slave_IFC (..),
14 FlexBus_Master_IFC (..),
17 // Higher-level enums and structs for the FlexBus
25 // Higher-level FIFO-like interfaces for the 5 AXI4 channels,
26 FlexBus_Register_IFC (..),
27 FlexBus_Register_Output_IFC (..),
28 FlexBus_Register_Input_IFC (..),
30 AXI4_Slave_to_FlexBus_Master_Xactor_IFC (..),
32 // Transactors from RTL-level interfacecs to FIFO-like interfaces.
33 mkAXI4_Slave_to_FlexBus_Master_Xactor;
35 // ================================================================
36 // BSV library imports
41 import SpecialFIFOs:: *;
42 import Connectable :: *;
43 import ConfigReg :: *;
44 `include "instance_defines.bsv"
47 // BSV additional libs
49 import Semi_FIFOF :: *;
50 import AXI4_Types :: *;
52 //import Memory_AXI4 :: *;
54 // ****************************************************************
55 // ****************************************************************
56 // Section: RTL-level interfaces
57 // ****************************************************************
58 // ****************************************************************
60 // ================================================================
61 // These are the signal-level interfaces for an FlexBus master.
62 // The (*..*) attributes ensure that when bsc compiles this to Verilog,
63 // we get exactly the signals specified in the FlexBus spec.
66 interface FlexBus_Master_IFC;
67 // FlexBus External Signals
69 // AD inout bus separate for now in BSV
70 interface Get#(Bit#(32)) m_AD; // out
71 interface Put#(Bit#(32)) m_din; // in
73 interface Get#(Bit#(1)) m_R_Wn; // out
74 interface Get#(Bit#(2)) m_TSIZ; // out
76 interface Get#(Bit#(6)) m_FBCSn; // out
77 interface Get#(Bit#(4)) m_BE_BWEn; // out
78 interface Get#(Bit#(1)) m_TBSTn; // out
79 interface Get#(Bit#(1)) m_OEn; // out
81 interface Get#(Bit#(1)) m_ALE; // out
82 interface Put#(Bit#(1)) tAn; // in
84 endinterface: FlexBus_Master_IFC
86 interface FlexBus_Register_Input_IFC;
87 method Action reset (Bit#(32) ad_bus);
88 method Action m_ad_bus (Bit#(32) ad_bus);
89 method Action m_data_bus (Bit#(32) data_bus);
90 endinterface: FlexBus_Register_Input_IFC
92 interface FlexBus_Register_Output_IFC;
93 (* always_ready, always_enabled *) method Bit#(6) m_FBCSn();
94 (* always_ready, always_enabled *) method Bit#(6) m_SWS();
95 (* always_ready, always_enabled *) method Bit#(1) m_SWS_EN();
96 (* always_ready, always_enabled *) method Bit#(2) m_ASET();
97 (* always_ready, always_enabled *) method Bit#(2) m_RDAH();
98 (* always_ready, always_enabled *) method Bit#(2) m_WRAH();
99 (* always_ready, always_enabled *) method Bit#(6) m_WS();
100 (* always_ready, always_enabled *) method Bit#(1) m_AA();
101 (* always_ready, always_enabled *) method Bit#(2) m_PS();
102 (* always_ready, always_enabled *) method Bit#(1) m_BEM();
103 (* always_ready, always_enabled *) method Bit#(1) m_BSTR();
104 (* always_ready, always_enabled *) method Bit#(1) m_BSTW();
105 endinterface: FlexBus_Register_Output_IFC
107 interface FlexBus_Register_IFC;
108 interface FlexBus_Register_Input_IFC inp_side;
109 interface FlexBus_Register_Output_IFC op_side;
110 endinterface: FlexBus_Register_IFC
112 // ================================================================
113 // These are the signal-level interfaces for an AXI4-Lite slave.
114 // The (*..*) attributes ensure that when bsc compiles this to Verilog,
115 // we get exactly the signals specified in the ARM spec.
116 interface FlexBus_Slave_IFC ;
119 (* result="AD" *) interface Put#(Bit#(32)) m_AD; // out
120 interface Get#(Bit#(32) m_din; // in
122 (* result="R_Wn" *) interface Put#(Bit#(1)) m_R_Wn; // out
123 (* result="TSIZ" *) interface Put#(Bit #(2) m_TSIZ; // out
125 (* result="FBCSn" *) interface Put#(Bit#(6)) m_FBCSn; // out
126 (* result="BEn_BWEn" *) interface Put#(Bit#(4)) m_BE_BWEn; // out
127 (* result="TBSTn" *) interface Put#(Bit#(1)) m_TBSTn; // out
128 (* result="OEn" *) interface Put#(Bit#(1)) m_OEn; // out
130 (* result="ALE" *) interface Put#(Bit#(1)) m_ALE; // out
131 interface Get#(Bit#(1) tAn; // in
134 (* always_ready, always_enabled *)
135 method Action m_AD ( (* port="AD" *) Bit #(32) i_AD); // in
138 (* always_ready, always_enabled *)
139 method Action m_ALE ( (* port="ALE" *) Bit #(1) i_ALE); // in
141 (* always_ready, always_enabled *)
142 method Action m_R_Wn ( (* port="R_Wn" *) Bit #(1) i_R_Wn); // in
143 (* always_ready, always_enabled *)
144 method Action m_TSIZ ( (* port="TSIZ" *) Bit #(2) i_TSIZ); // in
146 (* always_ready, always_enabled *)
147 method Action m_FBCSn ( (* port="FBCSn" *) Bit #(6) i_FBCSn); // in
148 (* always_ready, always_enabled *)
149 method Action m_BE_BWEn( (* port="BE_BWEn" *) Bit #(4) i_BE_BWEn); // in
150 (* always_ready, always_enabled *)
151 method Action m_TBSTn ( (* port="TBSTn" *) Bit #(1) i_TBSTn); // in
152 (* always_ready, always_enabled *)
153 method Action m_OEn ( (* port="OEn" *) Bit #(1) i_OEn); // in
155 (* always_ready, result="din" *)
156 method Bit #(32) m_din; // out
157 (* always_ready, result="TAn" *)
158 method Bit #(1) m_TAn; // out
160 endinterface: FlexBus_Slave_IFC
163 // ================================================================
164 // Connecting signal-level interfaces
166 `ifdef DISABLED_FOR_NOW // TODO. convert to get/put including slave ifc
167 instance Connectable #(FlexBus_Master_IFC ,
170 module mkConnection #(FlexBus_Master_IFC flexbus_m,
171 FlexBus_Slave_IFC flexbus_s)
174 (* fire_when_enabled, no_implicit_conditions *)
175 rule rl_flexbus_AD_signals;
176 flexbus_s.m_AD (flexbus_m.m_AD);
180 (* fire_when_enabled, no_implicit_conditions *)
181 rule rl_flexbus_Attr_signals;
182 flexbus_s.m_ALE (flexbus_m.m_ALE);
183 flexbus_s.m_R_Wn (flexbus_m.m_R_Wn);
184 flexbus_s.m_TSIZ (flexbus_m.m_TSIZ);
186 (* fire_when_enabled, no_implicit_conditions *)
187 rule rl_flexbus_signals;
188 flexbus_s.m_FBCSn (flexbus_m.m_FBCSn);
189 flexbus_s.m_BE_BWEn (flexbus_m.m_BE_BWEn);
190 flexbus_s.m_TBSTn (flexbus_m.m_TBSTn);
191 flexbus_s.m_OEn (flexbus_m.m_OEn);
193 (* fire_when_enabled *)
194 //(* fire_when_enabled, no_implicit_conditions *)
195 rule rl_flexbus_input_signals;
196 flexbus_m.m_din (flexbus_s.m_din);
197 flexbus_m.m_TAn (flexbus_s.m_TAn);
204 // ****************************************************************
205 // ****************************************************************
206 // Section: Higher-level FIFO-like interfaces and transactors
207 // ****************************************************************
208 // ****************************************************************
210 // ================================================================
211 // Higher-level types for payloads (rather than just bits)
213 typedef enum { IDLE, FlexBus_S0_DEQ_WR_FIFOS, FlexBus_S0_DEQ_RD_FIFOS, FlexBus_S1_ADDR, FlexBus_S2_WRITE, FlexBus_S3_BURST, FlexBus_S4_HOLD } FlexBus_States deriving (Bits, Eq, FShow);
214 typedef enum { IDLE, FlexBus_S0_CHK_FIFOS, FlexBus_S0_DEQ_FIFOS, FlexBus_WRITE_DUMMY1, FlexBus_WRITE_DUMMY2 } FlexBus_States_wr deriving (Bits, Eq, FShow);
215 typedef enum { IDLE, FlexBus_S0_CHK_FIFOS, FlexBus_S0_DEQ_FIFOS} FlexBus_States_rd deriving (Bits, Eq, FShow);
217 //FlexBus Addr. Data Payload
220 Bit #(32) s_AD; // out
222 deriving (Bits, FShow);
227 deriving (Bits, FShow);
232 Bit #(1) s_R_Wn; // out
233 Bit #(2) s_TSIZ; // out
235 deriving (Bits, FShow);
238 Bit #(6) s_FBCSn; // out
239 Bit #(4) s_BEn_BWEn; // out
240 Bit #(1) s_TBSTn; // out
241 Bit #(1) s_OEn; // out
242 } FlexBus_Signals #(numeric type wd_addr, numeric type wd_data)
243 deriving (Bits, FShow);
245 // FlexBus Control Signals
250 /* ----------------------------------------------------------------
252 module mkFlexBusTop (Empty);
253 AXI4_Slave_to_FlexBus_Master_Xactor_IFC#(56, 64,10)
254 flexbus_xactor_ifc <- mkAXI4_Slave_to_FlexBus_Master_Xactor;
259 // ---------------------------------------------------------------- */
260 // AXI4 Lite Slave to FlexBus Master transactor interface
262 interface AXI4_Slave_to_FlexBus_Master_Xactor_IFC #(numeric type wd_addr,
263 numeric type wd_data,
264 numeric type wd_user);
268 interface AXI4_Slave_IFC #(wd_addr, wd_data, wd_user) axi_side;
271 interface FlexBus_Master_IFC flexbus_side;
273 endinterface: AXI4_Slave_to_FlexBus_Master_Xactor_IFC
275 // ----------------------------------------------------------------
277 // AXI4 Lite Slave to FlexBus Master transactor
279 module mkAXI4_Slave_to_FlexBus_Master_Xactor
280 (AXI4_Slave_to_FlexBus_Master_Xactor_IFC #(wd_addr, wd_data, wd_user))
281 provisos (Add#(a__, 8, wd_addr),
282 Add#(b__, 64, wd_data),
283 //Bits#(Bit#(56), wd_addr),
284 //Bits#(Bit#(64), wd_data),
285 //Bits#(Bit#(32), wd_fb_addr),
286 //Bits#(Bit#(32), wd_fb_data),
287 //Bits#(Inout#(Bit#(32)), a__),
288 // Bits#(Inout#(Bit#(32)), wd_Fb_addr),
289 //Bits#(Inout#(Bit#(32)), 48),
290 Div#(wd_data, 16, 4));
291 Bool unguarded = True;
292 Bool guarded = False;
293 //let wD_FB_ADDR = valueOf(wd_fb_addr);
294 //let wD_FB_DATA = valueOf(wd_fb_data);
296 FlexBus_Register_IFC register_ifc <- mkFlexBus_Registers;
298 Reg#(Bit#(32)) r_AD <- mkReg(0);
299 Reg#(Bit#(32)) r_din <- mkReg(0);
300 Reg#(Bit#(1)) r_R_Wn <- mkReg(1'b1);
301 Reg#(Bit#(2)) r_TSIZ <- mkReg(2'b00);
302 Reg#(Bit#(6)) r_FBCSn <- mkReg(6'h3F);
303 Reg#(Bit#(4)) r_BE_BWEn <- mkReg(4'hF);
304 Reg#(Bit#(1)) r_TBSTn <- mkReg(1'b1);
305 Reg#(Bit#(1)) r_OEn <- mkReg(1'b1);
306 Reg#(Bit#(1)) r_ALE <- mkReg(1'b0);
307 Reg#(Bit#(1)) r_ext_TAn <- mkReg(1'b0);
308 Reg#(Bit#(1)) r_int_TAn <- mkReg(1'b1);
310 Reg#(Bit#(2)) r_ASET <- mkReg(2'b00);
311 Reg#(Bit#(2)) r_PS <- mkReg(2'b00);
312 Reg#(Bit#(3)) r_rpt_cnt <- mkReg(3'b000);
313 Reg#(Bit#(2)) r_burst_cnt <- mkReg(2'b00);
314 Reg#(Bit#(2)) r_hld_cnt <- mkReg(2'b00);
315 Reg#(Bit#(6)) r_WS_cnt <- mkReg(6'h00);
316 Reg#(Bit#(6)) r_SWS_cnt <- mkReg(6'h00);
317 Reg#(Bit#(wd_addr)) r_awaddr <- mkReg(0);
318 Reg#(Bit#(2)) r_awsize <- mkReg(0);
319 Reg#(Bit#(wd_addr)) r2_awaddr <- mkReg(0);
320 Reg#(Bit#(wd_data)) r_wdata <- mkReg(0);
321 Reg#(AXI4_Resp) r_wrbresp <- mkReg(AXI4_OKAY);
322 Reg#(AXI4_Resp) r_rresp <- mkReg(AXI4_OKAY);
323 Reg#(Bit#(wd_data)) r_rd_data <- mkReg(0);
324 Reg#(Bit#(TDiv#(wd_data,8))) r1_wstrb <- mkReg(0);
325 Reg#(Bit#(TDiv#(wd_data,8))) r2_wstrb <- mkReg(0);
326 Reg#(Bit#(wd_addr)) r_araddr <- mkReg(0);
327 Reg#(Bit#(wd_addr)) r2_araddr <- mkReg(0);
328 Reg#(Bit#(2)) r_arsize <- mkReg(0);
329 Reg#(Bit#(4)) r_arid <- mkReg(0);
330 Reg#(Bit#(4)) r_awid <- mkReg(0);
331 Reg#(Bit#(1)) wr_pending <- mkReg(0);
332 Reg#(Bit#(1)) r_chk_fifos_wr <- mkReg(0);
333 Reg#(Bit#(1)) r_chk_fifos_rd <- mkReg(0);
334 ConfigReg#(Bit#(1)) rd_wrb <- mkConfigReg(1);
335 Reg#(Bool) r_rready <- mkReg(False);
336 Reg#(Bool) r2_rready <- mkReg(False);
338 Reg#(Bool) r1_awvalid <- mkReg(False);
339 Reg#(Bool) r2_awvalid <- mkReg(False);
340 Reg#(Bool) r1_wvalid <- mkReg(False);
341 Reg#(Bool) r2_wvalid <- mkReg(False);
342 Reg#(Bool) r1_arvalid <- mkReg(False);
343 Reg#(Bool) r2_arvalid <- mkReg(False);
345 Reg#(Bool) r1_OEn <- mkReg(True);
347 Reg#(Bit#(8)) r_AD_32bit_data_byte1 <- mkReg(0);
348 Reg#(Bit#(8)) r_AD_32bit_data_byte2 <- mkReg(0);
349 Reg#(Bit#(8)) r_AD_32bit_data_byte3 <- mkReg(0);
350 Reg#(Bit#(8)) r_AD_32bit_data_byte4 <- mkReg(0);
352 Reg#(Bit#(8)) r_AD_32bit_addr_byte1 <- mkReg(0);
353 Reg#(Bit#(8)) r_AD_32bit_addr_byte2 <- mkReg(0);
354 Reg#(Bit#(8)) r_AD_32bit_addr_byte3 <- mkReg(0);
355 Reg#(Bit#(8)) r_AD_32bit_addr_byte4 <- mkReg(0);
357 Reg#(Bit#(8)) r_rd_data_32bit_byte1 <- mkReg(0);
358 Reg#(Bit#(8)) r_rd_data_32bit_byte2 <- mkReg(0);
359 Reg#(Bit#(8)) r_rd_data_32bit_byte3 <- mkReg(0);
360 Reg#(Bit#(8)) r_rd_data_32bit_byte4 <- mkReg(0);
362 Reg#(Bit#(32)) r_MBAR <- mkReg(32'h04000000);
364 Reg#(FlexBus_States) flexbus_state <- mkReg(IDLE);
365 Reg#(FlexBus_States_rd) flexbus_state_rd <- mkReg(FlexBus_S0_CHK_FIFOS);
366 Reg#(FlexBus_States_wr) flexbus_state_wr <- mkReg(FlexBus_S0_CHK_FIFOS);
368 // These FIFOs are guarded on BSV side, unguarded on AXI side
369 FIFOF #(AXI4_Wr_Addr #(wd_addr, wd_user)) f_wr_addr <- mkGFIFOF (unguarded, guarded);
370 FIFOF #(AXI4_Wr_Data #(wd_data)) f_wr_data <- mkGFIFOF (unguarded, unguarded);
371 FIFOF #(AXI4_Wr_Resp #(wd_user)) f_wr_resp <- mkGFIFOF (guarded, unguarded);
373 FIFOF #(AXI4_Rd_Addr #(wd_addr, wd_user)) f_rd_addr <- mkGFIFOF (unguarded, guarded);
374 FIFOF #(AXI4_Rd_Data #(wd_data, wd_user)) f_rd_data <- mkGFIFOF (guarded, unguarded);
376 Reg#(Maybe#(Bit#(1))) c_TAn[2] <- mkCReg(2, tagged Invalid);
377 Reg#(Maybe#(Bit#(32))) c_din[2] <- mkCReg(2, tagged Invalid);
379 //TriState#(Bit#(32)) tri_AD_out <- mkTriState(r1_OEn,r_AD);
381 // ----------------------------------------------------------------
390 rule rl_state_S0_CHK_FIFO_RD(flexbus_state_rd == FlexBus_S0_CHK_FIFOS);
391 `ifdef verbose_debug $display("STATE S0 CHK FIFOS RD FIRED"); `endif
392 if (f_rd_addr.notEmpty) begin
393 register_ifc.inp_side.m_ad_bus(f_rd_addr.first.araddr[31:0]);
394 flexbus_state_rd <= FlexBus_S0_DEQ_FIFOS;
395 `ifdef verbose_debug_l2 $display("READ ADDR FIFO WAS READ FIRST r_araddr=%h \n", f_rd_addr.first.araddr); `endif
399 (* preempts = "rl_check_read_fifo, rl_check_write_fifo" *)
400 rule rl_check_read_fifo (r_chk_fifos_rd == 1'b1 && f_rd_addr.notEmpty);
402 r_chk_fifos_rd <= 1'b0;
403 r_chk_fifos_wr <= 1'b0;
406 rule rl_check_write_fifo(r_chk_fifos_wr == 1'b1 && f_wr_addr.notEmpty && f_wr_data.notEmpty);
407 if (f_wr_addr.first.awaddr[31:16] != r_MBAR[31:16]) begin
409 r_chk_fifos_rd <= 1'b0;
410 r_chk_fifos_wr <= 1'b0;
414 rule rl_state_S0_CHK_FIFOS_WR(flexbus_state_wr == FlexBus_S0_CHK_FIFOS);
415 `ifdef verbose_debug $display("STATE S0 CHK FIFOS WR FIRED"); `endif
416 if (f_wr_addr.notEmpty && f_wr_data.notEmpty) begin
417 if (f_wr_addr.first.awaddr[31:16] == r_MBAR[31:16]) begin
418 f_wr_addr.deq; f_wr_data.deq;
421 flexbus_state_wr <= FlexBus_S0_DEQ_FIFOS;
423 register_ifc.inp_side.m_ad_bus(f_wr_addr.first.awaddr[31:0]);
424 register_ifc.inp_side.m_data_bus(f_wr_data.first.wdata[31:0]);
428 rule rl_state_S0_DEQ_FIFOS (flexbus_state_rd == FlexBus_S0_DEQ_FIFOS || flexbus_state_wr == FlexBus_S0_DEQ_FIFOS);
429 `ifdef verbose_debug $display("STATE S0 DEQ FIFOS FIRED"); `endif
430 if (rd_wrb == 1'b1) begin
431 flexbus_state <= FlexBus_S0_DEQ_RD_FIFOS;
432 flexbus_state_rd <= IDLE;
433 flexbus_state_wr <= IDLE;
435 else if (rd_wrb == 1'b0) begin
436 flexbus_state <= FlexBus_S0_DEQ_WR_FIFOS;
437 flexbus_state_rd <= IDLE;
438 flexbus_state_wr <= IDLE;
440 if (flexbus_state_rd == FlexBus_S0_DEQ_FIFOS && flexbus_state_wr == FlexBus_S0_DEQ_FIFOS) wr_pending <= 1'b1;
443 rule rl_state_S0_DEQ_WR_FIFOS (flexbus_state == FlexBus_S0_DEQ_WR_FIFOS);
444 `ifdef verbose_debug $display("STATE S0 DEQ WR FIFOS FIRED"); `endif
445 r_ASET <= register_ifc.op_side.m_ASET;
446 Bit#(3) v_awsize = 3'b000;
447 if ((f_wr_addr.notEmpty) ) begin
448 r1_awvalid <= f_wr_addr.notEmpty;
450 r_chk_fifos_wr <= 1'b1;
451 r_chk_fifos_rd <= 1'b1;
452 AXI4_Wr_Addr#(wd_addr, wd_user) wr_addr = f_wr_addr.first;
453 r_awaddr <= f_wr_addr.first.awaddr;
454 v_awsize = f_wr_addr.first.awsize;
455 r_awid <= f_wr_addr.first.awid;
456 case (v_awsize) matches
457 {3'b000}: r_awsize <= 2'b01;
458 {3'b001}: r_awsize <= 2'b10;
459 {3'b010}: r_awsize <= 2'b00;
461 `ifdef verbose_debug_l2 $display("ADDR FIFO WAS NOT EMPTY SO I DEQUEUED r_awaddr=%h \n", r_awaddr); `endif
463 if ((f_wr_data.notEmpty) ) begin
464 r1_wvalid <= f_wr_data.notEmpty;
466 `ifdef verbose_debug_l2 $display("DATA FIFO WAS NOT EMPTY SO I DEQUEUED\n"); `endif
467 AXI4_Wr_Data#(wd_data) wr_data = f_wr_data.first;
468 r_wdata <= f_wr_data.first.wdata;
469 r1_wstrb <= f_wr_data.first.wstrb;
470 `ifdef verbose_debug_l2 $display(" dequeued first r_wdata = %h", r_wdata); `endif
472 if (f_wr_addr.notEmpty && f_wr_data.notEmpty) begin
473 flexbus_state <= FlexBus_S1_ADDR;
477 rule rl_S0_DEQ_RD_FIFOS (flexbus_state == FlexBus_S0_DEQ_RD_FIFOS);
478 `ifdef verbose_debug $display("STATE S0 DEQ RD FIFOS FIRED"); `endif
479 r_ASET <= register_ifc.op_side.m_ASET;
480 Bit#(3) v_arsize = 3'b000;
481 if ((f_rd_addr.notEmpty) ) begin
482 r1_arvalid <= f_rd_addr.notEmpty;
484 r_chk_fifos_wr <= 1'b1;
485 r_chk_fifos_rd <= 1'b1;
486 AXI4_Rd_Addr#(wd_addr, wd_user) rd_addr = f_rd_addr.first;
487 r_araddr <= f_rd_addr.first.araddr;
488 v_arsize = f_rd_addr.first.arsize;
489 r_arid <= f_rd_addr.first.arid;
490 case (v_arsize) matches
491 {3'b000}: r_arsize <= 2'b01;
492 {3'b001}: r_arsize <= 2'b10;
493 {3'b010}: r_arsize <= 2'b00;
495 r_rd_data_32bit_byte1 <= 0;
496 r_rd_data_32bit_byte2 <= 0;
497 r_rd_data_32bit_byte3 <= 0;
498 r_rd_data_32bit_byte4 <= 0;
499 `ifdef verbose_debug_l2 $display("ADDR FIFO WAS NOT EMPTY SO I DEQUEUED r_araddr=%h \n", f_rd_addr.first.araddr); `endif
501 if (f_rd_addr.notEmpty) begin
502 flexbus_state <= FlexBus_S1_ADDR;
507 Bool bready = f_wr_resp.notFull;
508 if (f_wr_resp.notFull)
509 f_wr_resp.enq (AXI4_Wr_Resp {bresp:r_wrbresp,
516 Bool rready = f_rd_data.notFull;
517 if (f_rd_data.notFull && r2_rready) begin
518 f_rd_data.enq (AXI4_Rd_Data {rdata: r_rd_data,
523 //AXI4_Slave_IFC.m_rready(True);
524 `ifdef verbose_debug $display("RD DATA FIFO WAS NOT FULL SO I ENQUEUED r_rd_data=%h r2_rready= %b\n", r_rd_data, r2_rready); `endif
528 rule rl_state_S1_ADDR (flexbus_state == FlexBus_S1_ADDR); //Address state
529 `ifdef verbose_debug $display("STATE S1 FIRED");`endif
530 r_PS <= register_ifc.op_side.m_PS;
531 r_WS_cnt <= register_ifc.op_side.m_WS;
536 `ifdef verbose_debug_l2 $display(" r_ASET was ASSIGNED = %b", r_ASET); `endif
537 if (r_rpt_cnt == 3'b000) begin
538 if (r1_arvalid) begin
539 r_AD <= r_araddr[31:0];
540 r_R_Wn <= 1'b1; // Read
543 else if (r1_awvalid && r1_wvalid) begin
544 r_AD <= r_awaddr[31:0];
545 r_R_Wn <= 1'b0; // WriteBar
550 if (r_R_Wn == 1'b0) r_AD <= r_awaddr[31:0];
551 else r_AD <= r_araddr[31:0];
553 r_TSIZ <= register_ifc.op_side.m_PS;
555 if (( r_ASET != 2'b00) ) begin
556 r_ASET <= r_ASET - 1;
559 flexbus_state <= FlexBus_S2_WRITE;
560 if (r_rpt_cnt != 3'b000)
561 r_rpt_cnt <= r_rpt_cnt -1;
565 rule rl_assign_AD_bus_reg (flexbus_state == FlexBus_S1_ADDR) ; // Address an Attributes Phase
566 `ifdef verbose_debug_l2 $display(" ASSIGN AD BUS FIRED"); `endif
568 r2_awvalid <= r1_awvalid;
569 r2_wvalid <= r1_wvalid;
570 r2_wstrb <= r1_wstrb;
571 r2_arvalid <= r1_arvalid;
573 r2_araddr <= r_araddr;
574 r2_awaddr <= r_awaddr;
576 r_AD_32bit_data_byte1 <= pack(r_wdata[7:0]);
577 r_AD_32bit_data_byte2 <= pack(r_wdata[15:8]);
578 r_AD_32bit_data_byte3 <= pack(r_wdata[23:16]);
579 r_AD_32bit_data_byte4 <= pack(r_wdata[31:24]);
580 r_AD_32bit_addr_byte1 <= pack(r_awaddr[31:24]);
581 r_AD_32bit_addr_byte2 <= pack(r_awaddr[23:16]);
582 r_AD_32bit_addr_byte3 <= pack(r_awaddr[15:8]);
583 r_AD_32bit_addr_byte4 <= pack(r_awaddr[7:0]);
584 `ifdef verbose_debug_l2 $display("r_wdata after ASSIGN = %h r_PS = %b r_AD_32bit_data_byte1=%h ", r_wdata, r_PS, r_AD_32bit_data_byte1);
585 $display("r_awaddr after ASSIGN = %h r_PS = %b r_AD_32bit_addr_byte1=%h ", r_awaddr, r_PS, r_AD_32bit_addr_byte1); `endif
588 rule rl_assign_rd_data;
589 r_rd_data[63:0] <= pack({32'h00000000, r_rd_data_32bit_byte4, r_rd_data_32bit_byte3, r_rd_data_32bit_byte2, r_rd_data_32bit_byte1});
590 r2_rready <= r_rready;
591 `ifdef verbose_debug_l2 $display("ASSIGN READ DATA FIRED AND r_rd_data = %h r_rready=%b r2_rready=%b", r_rd_data, r_rready, r2_rready);`endif
594 rule rl_read_ext_signals;
595 if (isValid(c_TAn[1])) begin
596 r_ext_TAn <= fromMaybe(?,c_TAn[1]);
597 c_TAn[1]<= tagged Invalid;
599 if (isValid(c_din[1])) begin
600 r_din <= fromMaybe(?,c_din[1]);
601 c_din[1]<= tagged Invalid;
603 //r_din <= tri_AD_out._read;
606 rule rl_state_S2_WRITE (flexbus_state == FlexBus_S2_WRITE); //Write Phase
607 `ifdef verbose_debug $display("STATE S2 FIRED"); `endif
609 r_FBCSn <= register_ifc.op_side.m_FBCSn;
610 r_SWS_cnt <= register_ifc.op_side.m_SWS;
612 r_hld_cnt <= register_ifc.op_side.m_RDAH;
614 r_hld_cnt <= register_ifc.op_side.m_WRAH;
615 if (r_R_Wn == 1'b1) begin
617 if ((register_ifc.op_side.m_BSTR == 1'b1) && ((r_PS == 2'b01) || (r_PS == 2'b10) || (r_PS == 2'b11))) begin
622 // ASSIGN WRITE DATA DEPENDING ON BURST INHIBITED OR NOT
623 if ((r_rpt_cnt == 3'b000) ) begin
624 if (r_PS == 2'b01) begin
625 r_AD <= pack({r_AD_32bit_data_byte1,r_AD_32bit_addr_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
627 else if ((r_PS == 2'b10) || (r_PS == 2'b11)) begin
628 r_AD <= pack({r_AD_32bit_data_byte1,r_AD_32bit_data_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
631 r_AD <= pack({r_AD_32bit_data_byte1,r_AD_32bit_data_byte2,r_AD_32bit_data_byte3,r_AD_32bit_data_byte4});
634 else if (r_rpt_cnt == 3'b011) begin
635 r_AD <= pack({r_AD_32bit_data_byte2,r_AD_32bit_addr_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
637 else if (r_rpt_cnt == 3'b010)
638 r_AD <= pack({r_AD_32bit_data_byte3,r_AD_32bit_addr_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
639 else if (r_rpt_cnt == 3'b001) begin
640 if (r_awsize == 2'b00) begin
641 if ((r_PS == 2'b10) || (r_PS == 2'b11))
642 r_AD <= pack({r_AD_32bit_data_byte3,r_AD_32bit_data_byte4,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
643 else if ((r_PS == 2'b01))
644 r_AD <= pack({r_AD_32bit_data_byte4,r_AD_32bit_addr_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
646 else if (r_awsize == 2'b10) begin
647 if (r_PS == 2'b01) r_AD <= pack({r_AD_32bit_data_byte2,r_AD_32bit_addr_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
651 if (register_ifc.op_side.m_BEM == 1'b1)
652 r_BE_BWEn <= r2_wstrb[3:0];
653 if ((register_ifc.op_side.m_BSTW == 1'b1) && ((r_PS == 2'b01) || (r_PS == 2'b10) || (r_PS == 2'b11))) begin
657 if (r_WS_cnt == 6'h00) begin
658 if (r_ext_TAn == 1'b0) begin
660 flexbus_state <= FlexBus_S3_BURST;
662 if (register_ifc.op_side.m_AA == 1'b1) begin
665 r_WS_cnt <= register_ifc.op_side.m_WS;
666 if (r_R_Wn == 1'b1) begin
667 if (r_arsize == 2'b00) begin
668 if ((register_ifc.op_side.m_BSTR == 1'b1) && ((r_PS == 2'b01) || (r_PS == 2'b10) || (r_PS == 2'b11))) begin
669 if (r_PS == 2'b01) r_burst_cnt <= 2'b11;
670 if ((r_PS == 2'b10)||(r_PS == 2'b11)) r_burst_cnt <= 2'b01;
672 else if ((register_ifc.op_side.m_BSTR == 1'b0) && ((r_PS == 2'b01) || (r_PS == 2'b10) || (r_PS == 2'b11))) begin
673 if ((r_PS == 2'b01) && (r_rpt_cnt == 3'b000)) r_rpt_cnt <= 3'b100;
674 if (((r_PS == 2'b10)||(r_PS == 2'b11)) && (r_rpt_cnt == 3'b000)) r_rpt_cnt <= 3'b010;
677 else if (r_arsize == 2'b10) begin
678 if ((register_ifc.op_side.m_BSTR == 1'b1) && (r_PS == 2'b01)) begin
679 r_burst_cnt <= 2'b01;
681 else if ((register_ifc.op_side.m_BSTR == 1'b0) && (r_PS == 2'b01)) begin
682 if ((r_rpt_cnt == 3'b000)) r_rpt_cnt <= 3'b010;
687 if (r_awsize == 2'b00) begin
688 if ((register_ifc.op_side.m_BSTW == 1'b1) && ((r_PS == 2'b01) || (r_PS == 2'b10) || (r_PS == 2'b11))) begin
689 if (r_PS == 2'b01) r_burst_cnt <= 2'b11;
690 if ((r_PS == 2'b10)||(r_PS == 2'b11)) r_burst_cnt <= 2'b01;
692 else if ((register_ifc.op_side.m_BSTW == 1'b0) && ((r_PS == 2'b01) || (r_PS == 2'b10) || (r_PS == 2'b11))) begin
693 if ((r_PS == 2'b01) && (r_rpt_cnt == 3'b000)) r_rpt_cnt <= 3'b100;
694 if (((r_PS == 2'b10)||(r_PS == 2'b11)) && (r_rpt_cnt == 3'b000)) r_rpt_cnt <= 3'b010;
697 else if (r_awsize == 2'b10) begin
698 if ((register_ifc.op_side.m_BSTW == 1'b1) && (r_PS == 2'b01)) begin
699 r_burst_cnt <= 2'b01;
701 else if ((register_ifc.op_side.m_BSTW == 1'b0) && (r_PS == 2'b01)) begin
702 if ((r_rpt_cnt == 3'b000)) r_rpt_cnt <= 3'b010;
708 r_WS_cnt <= r_WS_cnt -1;
710 `ifdef verbose_debug_l2 $display("r_AD after WRITE = %h r_ASET=%b r_R_Wn= %b r_PS = %b r_AD_32bit_data_byte1=%h ", r_AD, r_ASET, r_R_Wn, r_PS, r_AD_32bit_data_byte1); `endif
713 rule rl_state_S3_BURST (flexbus_state == FlexBus_S3_BURST); // Data Phase with/without bursting terminated prematurely externally
714 `ifdef verbose_debug $display("STATE S3 FIRED"); `endif
715 `ifdef verbose_debug_l2
716 $display("r_rpt_cnt in BURST = %b", r_rpt_cnt);
717 $display("r_burst_cnt in BURST = %b, BSTW=%b", r_burst_cnt,register_ifc.op_side.m_BSTW);
718 $display (" r_AD in BURST = %h", r_AD);
719 $display("r_AD after WRITE = %h r_R_Wn= %b r_PS = %b r_AD_32bit_data_byte1=%h r_AD_32bit_data_byte2=%h r_AD_32bit_data_byte3=%h", r_AD, r_R_Wn, r_PS, r_AD_32bit_data_byte1,r_AD_32bit_data_byte2,r_AD_32bit_data_byte3);
721 if (r_ext_TAn == 1'b1) begin // premature external termination SLVERR response
722 flexbus_state <= FlexBus_S4_HOLD;
723 if (r_R_Wn == 1'b1) begin
724 r_rresp <= AXI4_SLVERR; //SLVERR
726 r_wrbresp <= AXI4_SLVERR; //SLVERR
729 else if (r_rpt_cnt == 3'b001) begin
730 if (r_R_Wn == 1'b1) begin
731 if (r_arsize == 2'b00) begin
732 if (r_PS == 2'b01) begin
733 r_rd_data_32bit_byte4 <= r_din[7:0];
735 else if ((r_PS == 2'b10) || (r_PS == 2'b11)) begin
736 r_rd_data_32bit_byte3 <= r_din[7:0];
737 r_rd_data_32bit_byte4 <= r_din[15:8];
740 else if (r_arsize == 2'b10) begin
742 r_rd_data_32bit_byte2 <= r_din[7:0];
745 //r_rpt_cnt <= r_rpt_cnt -1;
748 flexbus_state <= FlexBus_S4_HOLD;
749 if (register_ifc.op_side.m_AA == 1'b1) begin // check this functionality later for now
755 else if (r_rpt_cnt != 3'b000) begin
756 flexbus_state <= FlexBus_S1_ADDR;
757 r_ASET <= register_ifc.op_side.m_ASET;
758 if (register_ifc.op_side.m_AA == 1'b1) begin
763 if (r_R_Wn == 1'b1) begin
764 if ((r_PS == 2'b01) && (r_rpt_cnt == 3'b100))
765 r_rd_data_32bit_byte1 <= r_din[7:0];
766 else if ((r_PS == 2'b01) && (r_rpt_cnt == 3'b011))
767 r_rd_data_32bit_byte2 <= r_din[7:0];
768 else if ((r_PS == 2'b01) && (r_rpt_cnt == 3'b010)) begin
769 if (r_arsize == 2'b00)
770 r_rd_data_32bit_byte3 <= r_din[7:0];
771 else if (r_arsize == 2'b10)
772 r_rd_data_32bit_byte1 <= r_din[7:0];
774 else if ((r_PS == 2'b10) || (r_PS == 2'b11)) begin
775 r_rd_data_32bit_byte1 <= r_din[7:0];
776 r_rd_data_32bit_byte2 <= r_din[15:8];
780 else if (r_burst_cnt == 2'b01) begin
781 if (r_ext_TAn == 1'b1) begin
782 flexbus_state <= FlexBus_S4_HOLD;
785 if (r_R_Wn == 1'b0) begin
786 if (r_awsize == 2'b00) begin
788 r_AD <= pack({r_AD_32bit_data_byte4,r_AD_32bit_addr_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
789 else if ((r_PS == 2'b10) || (r_PS == 2'b11))
790 r_AD <= pack({r_AD_32bit_data_byte3,r_AD_32bit_data_byte4,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
792 // r_AD <= pack({r_AD_32bit_data_byte1,r_AD_32bit_data_byte2,r_AD_32bit_data_byte3,r_AD_32bit_data_byte4});
794 else if (r_awsize == 2'b10) begin
795 if (r_PS == 2'b01) r_AD <= pack({r_AD_32bit_data_byte2,r_AD_32bit_addr_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
799 if (r_arsize == 2'b00) begin
801 r_rd_data_32bit_byte3 <= r_din[7:0];
802 else if ((r_PS == 2'b10) || (r_PS == 2'b11)) begin
803 r_rd_data_32bit_byte1 <= r_din[7:0];
804 r_rd_data_32bit_byte2 <= r_din[15:8];
807 else if (r_arsize == 2'b10) begin
809 r_rd_data_32bit_byte1 <= r_din[7:0];
812 if (register_ifc.op_side.m_SWS_EN == 1'b1) begin
813 if (r_SWS_cnt == 6'h00) begin
814 r_SWS_cnt <= register_ifc.op_side.m_SWS;
815 if (register_ifc.op_side.m_AA == 1'b1) begin
821 r_burst_cnt <= r_burst_cnt -1;
822 //flexbus_state <= FlexBus_S4_HOLD;
825 r_SWS_cnt <= r_SWS_cnt -1;
829 if (r_WS_cnt == 6'h00) begin
830 r_WS_cnt <= register_ifc.op_side.m_WS;
831 if (register_ifc.op_side.m_AA == 1'b1) begin
837 r_burst_cnt <= r_burst_cnt -1;
838 //flexbus_state <= FlexBus_S4_HOLD;
841 r_WS_cnt <= r_WS_cnt - 1;
845 else if (r_burst_cnt != 2'b00) begin
846 if (r_R_Wn == 1'b0) begin
847 if ((r_PS == 2'b01) && (r_burst_cnt == 2'b11))
848 r_AD <= pack({r_AD_32bit_data_byte2,r_AD_32bit_addr_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
849 else if ((r_PS == 2'b01) && (r_burst_cnt == 2'b10)) begin
850 r_AD <= pack({r_AD_32bit_data_byte3,r_AD_32bit_addr_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
852 //else if ((r_PS == 2'b01) && (r_burst_cnt == 2'b01))
853 // r_AD <= pack({r_AD_32bit_data_byte3,r_AD_32bit_addr_byte2,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
854 //else if ((r_PS == 2'b10) || (r_PS == 2'b11))
855 // r_AD <= pack({r_AD_32bit_data_byte3,r_AD_32bit_data_byte4,r_AD_32bit_addr_byte3,r_AD_32bit_addr_byte4});
858 if ((r_PS == 2'b01) && (r_burst_cnt == 2'b11))
859 r_rd_data_32bit_byte1 <= r_din[7:0];
860 else if ((r_PS == 2'b01) && (r_burst_cnt == 2'b10)) begin
861 r_rd_data_32bit_byte2 <= r_din[7:0];
864 if (register_ifc.op_side.m_SWS_EN == 1'b1) begin
865 if (r_SWS_cnt == 6'h00) begin
866 r_SWS_cnt <= register_ifc.op_side.m_SWS;
867 if (register_ifc.op_side.m_AA == 1'b1)
869 r_burst_cnt <= r_burst_cnt -1;
872 r_SWS_cnt <= r_SWS_cnt -1;
876 if (r_WS_cnt == 6'h00) begin
877 r_WS_cnt <= register_ifc.op_side.m_WS;
878 if (register_ifc.op_side.m_AA == 1'b1)
880 r_burst_cnt <= r_burst_cnt -1;
883 r_WS_cnt <= r_WS_cnt - 1;
887 else if (r_burst_cnt == 2'b00) begin
888 flexbus_state <= FlexBus_S4_HOLD;
889 if (r_R_Wn == 1'b1) begin
890 if (r_arsize == 2'b00) begin
891 if (r_PS == 2'b01) begin
892 r_rd_data_32bit_byte4 <= r_din[7:0];
894 else if ((r_PS == 2'b10) || (r_PS == 2'b11)) begin
895 r_rd_data_32bit_byte3 <= r_din[7:0];
896 r_rd_data_32bit_byte4 <= r_din[15:8];
899 r_rd_data_32bit_byte1 <= r_din[7:0];
900 r_rd_data_32bit_byte2 <= r_din[15:8];
901 r_rd_data_32bit_byte3 <= r_din[23:16];
902 r_rd_data_32bit_byte4 <= r_din[31:24];
905 else if (r_arsize == 2'b10) begin
907 r_rd_data_32bit_byte2 <= r_din[7:0];
908 //if ((r_PS == 2'b10) || (r_PS == 2'b11)) begin
910 r_rd_data_32bit_byte1 <= r_din[7:0];
911 r_rd_data_32bit_byte2 <= r_din[15:8];
914 else if (r_arsize == 2'b01) begin
915 r_rd_data_32bit_byte1 <= r_din[7:0];
919 if (register_ifc.op_side.m_AA == 1'b1) begin // check this functionality later for now
927 rule rl_state_S4_HOLD (flexbus_state == FlexBus_S4_HOLD); //Address Phase
928 `ifdef verbose_debug $display("STATE S4 FIRED");`endif
935 if (r_hld_cnt == 2'b00) begin
936 if (wr_pending == 1'b1) begin
937 flexbus_state <= FlexBus_S0_DEQ_WR_FIFOS;
938 flexbus_state_wr <= IDLE;
939 flexbus_state_rd <= IDLE;
943 flexbus_state <= IDLE;
944 flexbus_state_wr <= FlexBus_S0_CHK_FIFOS;
945 flexbus_state_rd <= FlexBus_S0_CHK_FIFOS;
952 r_wrbresp <= AXI4_OKAY;
953 r_rresp <= AXI4_OKAY;
956 r_burst_cnt <= 2'b00;
968 r_hld_cnt <= r_hld_cnt -1;
971 // ----------------------------------------------------------------
975 `ifdef verbose_debug_l2 $display (" I RESET \n"); `endif
982 c_TAn[0]<= tagged Invalid;
983 c_din[0]<= tagged Invalid;
987 interface axi_side = interface AXI4_Slave_IFC;
990 method Action m_awvalid (Bool awvalid,
991 Bit #(wd_addr) awaddr,
993 Bit #(wd_user) awuser,
998 if (awvalid && f_wr_addr.notFull) begin
999 f_wr_addr.enq (AXI4_Wr_Addr {awaddr: awaddr,
1008 method Bool m_awready;
1009 return f_wr_addr.notFull;
1013 method Action m_wvalid (Bool wvalid,
1014 Bit #(wd_data) wdata,
1015 Bit #(TDiv #(wd_data, 8)) wstrb,
1018 if (wvalid && f_wr_data.notFull) begin
1019 f_wr_data.enq (AXI4_Wr_Data {wdata: wdata, wstrb: wstrb, wlast:wlast, wid: wid});
1023 method Bool m_wready;
1024 return f_wr_data.notFull;
1027 // Wr Response channel
1028 method Bool m_bvalid = f_wr_resp.notEmpty;
1029 method Bit #(2) m_bresp = pack (f_wr_resp.first.bresp);
1030 method Bit #(wd_user) m_buser = f_wr_resp.first.buser;
1031 method Bit #(4) m_bid = f_wr_resp.first.bid;
1032 method Action m_bready (Bool bready);
1033 if (bready && f_wr_resp.notEmpty)
1038 method Action m_arvalid (Bool arvalid,
1039 Bit #(wd_addr) araddr,
1041 Bit #(wd_user) aruser,
1045 if (arvalid && f_rd_addr.notFull) begin
1046 f_rd_addr.enq (AXI4_Rd_Addr {araddr: araddr,
1055 method Bool m_arready;
1056 return f_rd_addr.notFull;
1060 method Bool m_rvalid = f_rd_data.notEmpty;
1061 method Bit #(2) m_rresp = pack (f_rd_data.first.rresp);
1062 method Bit #(wd_data) m_rdata = f_rd_data.first.rdata;
1063 method Bool m_rlast = f_rd_data.first.rlast;
1064 method Bit #(wd_user) m_ruser = f_rd_data.first.ruser;
1065 method Bit#(4) m_rid=f_rd_data.first.rid;
1067 method Action m_rready (Bool rready);
1068 if (rready && f_rd_data.notEmpty)
1073 interface flexbus_side = interface FlexBus_Master_IFC;
1074 //interface io_AD_master = tri_AD_out.io;
1076 interface tAn = interface Put
1077 method Action put(Bit#(1) in) if(c_TAn[0] matches tagged Invalid);
1078 c_TAn[0] <= tagged Valid in;
1082 interface m_din = interface Put
1083 method Action put(Bit#(32) in) if(c_din[0] matches tagged Invalid);
1084 c_din[0] <= tagged Valid in;
1088 interface m_AD = interface Get
1089 method ActionValue#(Bit#(32)) get;
1094 interface m_R_Wn = interface Get
1095 method ActionValue#(Bit#(1)) get;
1100 interface m_TSIZ = interface Get
1101 method ActionValue#(Bit#(2)) get;
1106 interface m_FBCSn = interface Get
1107 method ActionValue#(Bit#(6)) get;
1112 interface m_BE_BWEn = interface Get
1113 method ActionValue#(Bit#(4)) get;
1118 interface m_TBSTn = interface Get
1119 method ActionValue#(Bit#(1)) get;
1124 interface m_OEn = interface Get
1125 method ActionValue#(Bit#(1)) get;
1130 interface m_ALE = interface Get
1131 method ActionValue#(Bit#(1)) get;
1140 endmodule: mkAXI4_Slave_to_FlexBus_Master_Xactor
1142 module mkFlexBus_Registers (FlexBus_Register_IFC);
1144 // Vectors of Chip Select AR, MR and Control Registers
1145 Vector#(6, Reg#(Bit#(32)) ) vec_addr_regs <- replicateM (mkReg(0));
1146 Vector#(6, Reg#(Bit#(32)) ) vec_mask_regs <- replicateM (mkReg(0));
1147 Vector#(6, Reg#(Bit#(32)) ) vec_cntr_regs <- replicateM (mkReg(0));
1149 // Control Register Fields
1151 Reg#(Bit#(6)) r_FBCSn <- mkReg(6'h3F);
1152 Reg#(Bit#(6)) r_SWS <- mkReg(6'h00);
1153 Reg#(Bit#(1)) r_SWS_EN <- mkReg(1'b0);
1154 Reg#(Bit#(2)) r_ASET <- mkReg(2'b00);
1155 Reg#(Bit#(2)) r_RDAH <- mkReg(2'b00);
1156 Reg#(Bit#(2)) r_WRAH <- mkReg(2'b00);
1157 Reg#(Bit#(6)) r_WS <- mkReg(6'h00);
1158 Reg#(Bit#(1)) r_AA <- mkReg(1'b0);
1159 Reg#(Bit#(2)) r_PS <- mkReg(2'b00);
1160 Reg#(Bit#(1)) r_BEM <- mkReg(1'b0);
1161 Reg#(Bit#(1)) r_BSTR <- mkReg(1'b0);
1162 Reg#(Bit#(1)) r_BSTW <- mkReg(1'b0);
1164 Reg#(Bit#(32)) r_rom_cntr_reg_0 <- mkReg(0);
1165 Reg#(Bit#(32)) r_ad_bus <- mkReg(32'hFFFFFFFF);
1166 Reg#(Bit#(32)) r_data_bus <- mkReg(32'h00000000);
1167 Reg#(Bit#(32)) r_MBAR <- mkReg(32'h04000000);
1168 //------------------------------------------------------------------------
1170 rule rl_write_config_regs;
1171 Bit#(32) v_MBAR = r_MBAR + 'h0500;
1172 for (int i=0; i<6; i=i+1) begin
1173 if ( v_MBAR == r_ad_bus) begin
1174 vec_addr_regs[i][31:16] <= r_data_bus[31:16];
1176 v_MBAR = v_MBAR + 'h04;
1177 if ( v_MBAR == r_ad_bus) begin
1178 vec_mask_regs[i] <= r_data_bus;
1180 v_MBAR = v_MBAR + 'h04;
1181 if ( v_MBAR == r_ad_bus) begin
1182 vec_cntr_regs[i] <= r_data_bus;
1184 v_MBAR = v_MBAR + 'h04;
1188 rule rl_generate_individual_chip_sels;
1190 Bit#(6) chp_sel_vec = 6'h3F;
1191 Bit#(32) r_cntr_reg_sel = 32'h00000000;
1192 for (int i=0; i<6; i=i+1) begin
1193 if ((~vec_mask_regs[i] & vec_addr_regs[i]) == (~vec_mask_regs[i] & pack({r_ad_bus[31:16],16'h0000}))) begin
1194 chp_sel_vec[i] = 1'b0;
1197 r_FBCSn <= pack({chp_sel_vec[5],chp_sel_vec[4],chp_sel_vec[3],chp_sel_vec[2],chp_sel_vec[1],chp_sel_vec[0]});
1199 case (pack({chp_sel_vec[5],chp_sel_vec[4],chp_sel_vec[3],chp_sel_vec[2],chp_sel_vec[1],chp_sel_vec[0]})) matches
1200 {6'b111110}: r_cntr_reg_sel = vec_cntr_regs[0];
1201 {6'b111101}: r_cntr_reg_sel = vec_cntr_regs[1];
1202 {6'b111011}: r_cntr_reg_sel = vec_cntr_regs[2];
1203 {6'b110111}: r_cntr_reg_sel = vec_cntr_regs[3];
1204 {6'b101111}: r_cntr_reg_sel = vec_cntr_regs[4];
1205 {6'b011111}: r_cntr_reg_sel = vec_cntr_regs[5];
1208 r_SWS <= r_cntr_reg_sel[31:26];
1209 r_SWS_EN <= r_cntr_reg_sel[23];
1210 r_ASET <= r_cntr_reg_sel[21:20];
1211 r_RDAH <= r_cntr_reg_sel[19:18];
1212 r_WRAH <= r_cntr_reg_sel[17:16];
1213 //r_WS <= r_cntr_reg_sel[15:10];
1215 r_AA <= r_cntr_reg_sel[8];
1216 r_PS <= r_cntr_reg_sel[7:6];
1217 r_BEM <= r_cntr_reg_sel[5];
1218 r_BSTR <= r_cntr_reg_sel[4];
1219 r_BSTW <= r_cntr_reg_sel[3];
1221 //-------------------------------------------------------------------------
1222 // FlexBus Register Input Interface
1223 interface inp_side = interface FlexBus_Register_Input_IFC;
1224 method Action reset (Bit #(32) ad_bus);
1225 for (int i=0; i<6; i=i+1)
1226 vec_addr_regs[i] <= 32'h00000000;
1227 for (int i=0; i<6; i=i+1)
1228 vec_mask_regs[i] <= 32'h00000000;
1229 for (int i=0; i<6; i=i+1)
1230 vec_cntr_regs[i] <= 32'h00000000;
1231 r_rom_cntr_reg_0[8] <= ad_bus[2];
1232 r_rom_cntr_reg_0[7:6] <= ad_bus[1:0];
1233 r_rom_cntr_reg_0[5] <= ad_bus[3];
1234 r_rom_cntr_reg_0[15:10] <= 6'h3F;
1235 r_rom_cntr_reg_0[21:16] <= 6'h3F;
1236 vec_cntr_regs[0] <= r_rom_cntr_reg_0;
1238 method Action m_ad_bus (Bit #(32) ad_bus);
1241 method Action m_data_bus (Bit #(32) data_bus);
1242 r_data_bus <= data_bus;
1246 // FlexBus Register Output Interface
1247 interface op_side = interface FlexBus_Register_Output_IFC;
1248 method Bit#(6) m_FBCSn ();
1251 method Bit#(6) m_SWS ();
1254 method Bit#(1) m_SWS_EN ();
1257 method Bit#(2) m_ASET ();
1260 method Bit#(2) m_RDAH ();
1263 method Bit#(2) m_WRAH ();
1266 method Bit#(6) m_WS ();
1269 method Bit#(1) m_AA ();
1272 method Bit#(2) m_PS ();
1275 method Bit#(1) m_BEM ();
1278 method Bit#(1) m_BSTR ();
1281 method Bit#(1) m_BSTW ();
1286 endmodule: mkFlexBus_Registers
1289 module mkVerfn_Top (Empty);
1292 FlexBus_Slave_to_AXI4_Master_Fabric_IFC#(32,32,4)
1293 verfn_ifc <- mkFlexBus_Slave_to_AXI4_Master_Fabric;
1294 AXI4_Slave_to_FlexBus_Master_Xactor_IFC#(32, 32, 4)
1295 flexbus_xactor_ifc <- mkAXI4_Slave_to_FlexBus_Master_Xactor;
1297 mkConnection(flexbus_xactor_ifc.flexbus_side,verfn_ifc.flexbus_side);
1300 AXI4_Slave_to_FlexBus_Master_Xactor_IFC#(56, 64,10)
1301 flexbus_xactor_ifc <- mkAXI4_Slave_to_FlexBus_Master_Xactor;