2 Copyright (c) 2013, IIT Madras
5 Redistribution and use in source and binary forms, with or without
6 modification, are permitted provided that the following conditions
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10 this list of conditions and the following disclaimer.
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12 this list of conditions and the following disclaimer in the documentation
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18 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19 "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20 LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
21 A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
22 HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
23 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
24 TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
25 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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27 NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 -------------------------------------------------------------------------------------------------
31 Code inpired by the pwm module at: https://github.com/freecores/pwm
36 /*=== Project imports ==*/
38 /*======================*/
39 /*== Package imports ==*/
40 //import defined_types::*;
41 `include "instance_defines.bsv"
47 import AXI4_Lite_Types::*;
52 /*======================*/
54 interface UserInterface;
55 method ActionValue#(Bool) write(Bit#(`PADDR) addr, Bit#(`Reg_width) data);
56 method Tuple2#(Bool, Bit#(`Reg_width)) read(Bit#(`PADDR) addr);
64 interface UserInterface user;
69 module mkPWM#(Clock ext_clock)(PWM);
71 let bus_clock <- exposeCurrentClock;
72 let bus_reset <- exposeCurrentReset;
74 Reg#(Bit#(`PWMWIDTH)) period <- mkReg(0);
75 Reg#(Bit#(`PWMWIDTH)) duty_cycle <- mkReg(0);
76 Reg#(Bit#(`PWMWIDTH)) clock_divisor <- mkReg(0);
77 // =========== Control registers ================== //
78 Reg#(Bit#(1)) clock_selector <- mkReg(0); // bit-0
79 Reg#(Bit#(1)) pwm_enable <- mkReg(0); // bit-1
80 Reg#(Bit#(1)) pwm_start <- mkReg(0); // bit-2
81 Reg#(Bit#(1)) continous_once <- mkReg(0); // bit-3
82 Reg#(Bit#(1)) pwm_output_enable <- mkReg(0); // bit-4
83 Reg#(Bit#(1)) interrupt <- mkReg(0); // bit-5
84 Reg#(Bit#(1)) reset_counter <- mkReg(0); // bit-7
85 Reg#(Bit#(8)) control = concatReg8(reset_counter, readOnlyReg(0),
86 readOnlyReg(interrupt),
87 pwm_output_enable, continous_once,
88 pwm_start, pwm_enable,
90 // ================================================ //
92 // Generate a reset signal is there is a reset from
93 // the bus interface of if the reset_counter
94 // bit in the control register is set. The new reset
95 // is called overall_reset. Only the counter
96 // and the output signals need to be reset by this.
97 MakeResetIfc control_reset <- mkReset(1,False, bus_clock);
100 control_reset.assertReset;
102 Reset overall_reset <- mkResetEither(bus_reset,control_reset.new_rst);
104 // Select between bus clock or external clock
105 MuxClkIfc clock_selection <- mkUngatedClockMux(ext_clock,bus_clock);
106 Reset async_reset <- mkAsyncResetFromCR(0,clock_selection.clock_out);
107 rule select_busclk_extclk;
108 clock_selection.select(clock_selector==1);
111 // The following register is required to transfer
112 // the divisor value from bus_clock to
113 // external clock domain. This is necessary if the
114 // clock divider needs to operate on the
115 // external clock. In this case, the divisor value
116 // should also come from the same clock domain.
117 Reg#(Bit#(`PWMWIDTH)) clock_divisor_sync <- mkSyncRegFromCC(0,
118 clock_selection.clock_out);
119 rule transfer_data_from_clock_domains;
120 clock_divisor_sync <= clock_divisor;
123 // The PWM can operate on a slowed-down clock.
124 // The following module generates a slowed-down
125 // clock based on the value given in register divisor.
126 // Since the clock_divider works on a muxed
127 // clock domain of the external clock or bus_clock,
128 // the divisor (which operates on the bus_clock
129 // will have to be synchronized and sent to the divider
130 Ifc_ClockDiv#(`PWMWIDTH) clock_divider <- mkClockDiv(
131 clocked_by clock_selection.clock_out,
132 reset_by async_reset);
133 let downclock = clock_divider.slowclock;
134 Reset downreset <- mkAsyncReset(0,overall_reset,downclock);
135 rule generate_slow_clock;
136 clock_divider.divisor(clock_divisor_sync);
139 // ======= Actual Counter and PWM signal generation ======== //
140 Reg#(Bit#(1)) pwm_output <- mkReg(0,clocked_by downclock,
142 Reg#(Bit#(`PWMWIDTH)) rg_counter <-mkReg(0,clocked_by downclock,
145 // create synchronizers for clock domain crossing.
146 Reg#(Bit#(1)) sync_pwm_output <- mkSyncRegToCC(0,downclock,downreset);
147 ReadOnly#(Bit#(1)) pwm_signal <- mkNullCrossingWire(bus_clock, pwm_output);
148 Reg#(Bit#(1)) sync_continous_once <- mkSyncRegFromCC(0,downclock);
149 Reg#(Bit#(`PWMWIDTH)) sync_duty_cycle <- mkSyncRegFromCC(0,downclock);
150 Reg#(Bit#(`PWMWIDTH)) sync_period <- mkSyncRegFromCC(0,downclock);
151 Reg#(Bit#(1)) sync_pwm_enable <- mkSyncRegFromCC(0,downclock);
152 Reg#(Bit#(1)) sync_pwm_start <- mkSyncRegFromCC(0,downclock);
153 rule sync_pwm_output_to_default_clock;
154 sync_pwm_output <= pwm_output;
157 // capture the synchronized values from the default
158 // clock domain to the downclock domain for
159 // actual timer and pwm functionality.
160 rule sync_from_default_to_downclock;
161 sync_continous_once <= continous_once;
162 sync_duty_cycle <= duty_cycle;
163 sync_period <= period;
164 sync_pwm_enable <= pwm_enable;
165 sync_pwm_start <= pwm_start;
167 let temp = sync_period==0?0:sync_period-1;
169 // This rule generates the interrupt in the timer
170 // mode and resets it if the user-write interface
171 // writes a value of 1 to the reset_counter bit.
172 rule generate_interrupt_in_timer_mode;
174 interrupt <= sync_pwm_output;
175 else if(reset_counter==1)
181 // This rule performs the actual pwm and the timer
182 // functionality. if pwm_enable is 1 then the
183 // PWM mode is selected. Every time the counter
184 // value equals/crosses the period value it is
185 // reset and the output pwm_output signal is toggled.
186 // The timer mode is selected when pwm_enable is 0.
187 // Here again 2 more modes are possible. if the
188 // continous_once bit is 0 then the timer is in one time.
189 // In this case once the counter reaches
190 // the period value it raises an interrupt and
191 // stops the counter. In the continuous mode
192 // however, when the counter reaches the period value
193 // the interrupt is raise, the counter is
194 // reset to 0 and continues counting.
195 // During continuous counting the interrupt can be cleared by
196 // the user but will be set back when the counter reaches the period value.
197 rule compare_and_generate_pwm(sync_pwm_start==1);
198 let cntr = rg_counter+1;
199 if(sync_pwm_enable==1)begin // PWM mode enabled
200 if(rg_counter >= temp)
204 if(rg_counter < sync_duty_cycle)
209 else begin // Timer mode enabled.
210 if(sync_continous_once==0) begin // One time mode.
211 if(rg_counter >= temp)begin
217 else begin // Continous mode.
218 if(rg_counter >= temp)begin
229 // ========================================================= //
230 interface user = interface UserInterface
231 method ActionValue#(Bool) write(Bit#(`PADDR) addr, Bit#(`Reg_width) data);
234 0: period <= truncate(data);
235 1: duty_cycle <= truncate(data);
236 2: begin control <= truncate(data);end
237 3: clock_divisor <= truncate(data);
243 method Tuple2#(Bool, Bit#(`Reg_width)) read(Bit#(`PADDR) addr);
245 Bit#(`Reg_width) data;
247 0: data = zeroExtend(period);
248 1: data = zeroExtend(duty_cycle);
249 2: data = zeroExtend(control);
250 3: data = zeroExtend(clock_divisor);
251 default: begin err = True; data = 0; end
253 return tuple2(err,data);
256 interface io = interface PWMIO
257 method pwm_o=pwm_output_enable==1?pwm_signal:0;
262 // the following interface and module will add the
263 // AXI4Lite interface to the PWM module
264 interface Ifc_PWM_bus;
265 interface PWMIO pwm_io;
266 interface AXI4_Lite_Slave_IFC#(`PADDR, `Reg_width,
267 `USERSPACE) axi4_slave;
271 module mkPWM_bus#(Clock ext_clock)(Ifc_PWM_bus);
272 PWM pwm <-mkPWM(ext_clock);
273 AXI4_Lite_Slave_Xactor_IFC#(`PADDR,`Reg_width, `USERSPACE)
274 s_xactor<-mkAXI4_Lite_Slave_Xactor();
277 let req <- pop_o (s_xactor.o_rd_addr);
278 let {err,data} = pwm.user.read(req.araddr);
279 let resp= AXI4_Lite_Rd_Data {rresp:err?
280 AXI4_LITE_SLVERR:AXI4_LITE_OKAY,
281 rdata:data, ruser: ?};
282 s_xactor.i_rd_data.enq(resp);
286 let addreq <- pop_o(s_xactor.o_wr_addr);
287 let datareq <- pop_o(s_xactor.o_wr_data);
288 let err <- pwm.user.write(addreq.awaddr, datareq.wdata);
289 let resp = AXI4_Lite_Wr_Resp {bresp: err?
290 AXI4_LITE_SLVERR:AXI4_LITE_OKAY,
292 s_xactor.i_wr_resp.enq(resp);
295 interface pwm_io = pwm.io;
296 interface axi4_slave = s_xactor.axi_side;
301 // the following interface and module will add the
302 // AXI4 interface to the PWM module
303 interface Ifc_PWM_bus;
304 interface PWMIO pwm_io;
305 interface AXI4_Slave_IFC#(`PADDR, `Reg_width,`USERSPACE) axi4_slave;
309 module mkPWM_bus#(Clock ext_clock)(Ifc_PWM_bus);
310 PWM pwm <-mkPWM(ext_clock);
311 AXI4_Slave_Xactor_IFC#(`PADDR,`Reg_width,
312 `USERSPACE) s_xactor<-mkAXI4_Slave_Xactor();
315 let req <- pop_o (s_xactor.o_rd_addr);
316 let {err,data} = pwm.user.read(req.araddr);
317 if(!(req.arsize == 2 && req.arlen == 0))
319 let resp= AXI4_Rd_Data {rresp:err?AXI4_SLVERR:AXI4_OKAY,
321 ?, rid:req.arid, rlast: True};
322 s_xactor.i_rd_data.enq(resp);
326 let addreq <- pop_o(s_xactor.o_wr_addr);
327 let datareq <- pop_o(s_xactor.o_wr_data);
328 let err <- pwm.user.write(addreq.awaddr, datareq.wdata);
329 if(!(addreq.awsize == 2 && addreq.awlen == 0))
331 let resp = AXI4_Wr_Resp {bresp: err?AXI4_SLVERR:AXI4_OKAY, buser: ?,
333 s_xactor.i_wr_resp.enq(resp);
336 interface pwm_io = pwm.io;
342 let clk <- exposeCurrentClock;
343 PWM pwm <- mkPWM(clk, 32);
344 Reg#(Bit#(5)) rg_state <- mkReg(0);
346 rule state1(rg_state==0);
348 let x <- pwm.user.write(0,'d4);
350 rule state2(rg_state==1);
352 let x <- pwm.user.write('d4,'d3);
354 rule state3(rg_state==2);
356 let x <- pwm.user.write('hc,'d4);
358 rule state4(rg_state==3);
360 let x <- pwm.user.write(8,'b0001_0110);