fa7e3a7a617e2547004f4f753d39152c2a76f91d
[pinmux.git] / src / pinmux_generator.py
1 # ================================== Steps to add peripherals ============
2 # Step-1: create interface declaration for the peripheral to be added.
3 # Remember these are interfaces defined for the pinmux and hence
4 # will be opposite to those defined at the peripheral.
5 # For eg. the output TX from the UART will be input (method Action)
6 # for the pinmux.
7 # These changes will have to be done in interface_decl.py
8 # Step-2 define the wires that will be required to transfer data from the
9 # peripheral interface to the IO cell and vice-versa. Create a
10 # mkDWire for each input/output between the peripheral and the
11 # pinmux. Also create an implicit wire of GenericIOType for each cell
12 # that can be connected to a each bit from the peripheral.
13 # These changes will have to be done in wire_def.py
14 # Step-3: create the definitions for each of the methods defined above.
15 # These changes will have to be done in interface_decl.py
16 # ========================================================================
17
18 # default module imports
19 import os
20 import sys
21 import time
22 import math
23
24 # project module imports
25 from interface_decl import Interfaces, mux_interface, io_interface
26 from wire_def import muxwire, generic_io
27 from parse import Parse
28 from actual_pinmux import init
29 from bus_transactors import axi4_lite
30
31 p = Parse()
32 init(p)
33 ifaces = Interfaces()
34 #ifaces.ifaceadd('io', p.N_IO, io_interface)
35
36 if not os.path.exists("bsv_src"):
37 os.makedirs("bsv_src")
38
39 copyright = '''
40 /*
41 This BSV file has been generated by the PinMux tool available at:
42 https://bitbucket.org/casl/pinmux.
43
44 Authors: Neel Gala, Luke
45 Date of generation: ''' + time.strftime("%c") + '''
46 */
47 '''
48 header = copyright+'''
49 package pinmux;
50
51 typedef struct{
52 Bit#(1) outputval; // output from core to pad bit7
53 Bit#(1) output_en; // output enable from core to pad bit6
54 Bit#(1) input_en; // input enable from core to io_cell bit5
55 Bit#(1) pullup_en; // pullup enable from core to io_cell bit4
56 Bit#(1) pulldown_en; // pulldown enable from core to io_cell bit3
57 Bit#(1) drivestrength; // drivestrength from core to io_cell bit2
58 Bit#(1) pushpull_en; // pushpull enable from core to io_cell bit1
59 Bit#(1) opendrain_en; // opendrain enable form core to io_cell bit0
60 } GenericIOType deriving(Eq,Bits,FShow);
61
62 interface MuxSelectionLines;
63 '''
64 footer = '''
65 endinterface;
66 endmodule
67 endpackage
68 '''
69 # ============================================#
70 # ==== populating the file with the code =====#
71 # ============================================#
72
73 # package and interface declaration followed by the generic io_cell definition
74 with open("./bsv_src/pinmux.bsv", "w") as bsv_file:
75 bsv_file.write(header)
76
77 bsv_file.write('''
78
79 // declare the method which will capture the user pin-mux
80 // selection values.The width of the input is dependent on the number
81 // of muxes happening per IO. For now we have a generalized width
82 // where each IO will have the same number of muxes.''')
83
84 for cell in p.muxed_cells:
85 bsv_file.write(mux_interface.ifacefmt(cell[0],
86 int(math.log(len(cell) - 1, 2))))
87
88 bsv_file.write('''
89 endinterface
90
91 interface PeripheralSide;
92 // declare the interface to the IO cells.
93 // Each IO cell will have 8 input field (output from pin mux
94 // and on output field (input to pinmux)''')
95 for i in range(0, p.N_IO):
96 bsv_file.write('''\n // interface declaration between IO-{0} and pinmux'''.format(i))
97
98 bsv_file.write(io_interface.ifacefmt(i))
99 # ==============================================================
100
101 # == create method definitions for all peripheral interfaces ==#
102 ifaces.ifacefmt(bsv_file)
103
104 # ==============================================================
105
106 # ===== finish interface definition and start module definition=======
107 bsv_file.write('''
108 endinterface
109
110 interface Ifc_pinmux;
111 interface MuxSelectionLines mux_lines;
112 interface PeripheralSide peripheral_side;
113 endinterface
114 (*synthesize*)
115 module mkpinmux(Ifc_pinmux);
116 ''')
117 # ====================================================================
118
119 # ======================= create wire and registers =================#
120 bsv_file.write('''
121 // the followins wires capture the pin-mux selection
122 // values for each mux assigned to a CELL
123 ''')
124 for cell in p.muxed_cells:
125 bsv_file.write(muxwire.format(
126 cell[0], int(math.log(len(cell) - 1, 2))))
127
128 bsv_file.write(
129 '''\n // following wires capture the values sent to the IO Cell''')
130 for i in range(0, p.N_IO):
131 bsv_file.write(generic_io.format(i))
132
133 ifaces.wirefmt(bsv_file)
134
135 bsv_file.write("\n")
136 # ====================================================================
137 # ========================= Actual pinmuxing ========================#
138 bsv_file.write('''
139 /*====== This where the muxing starts for each io-cell======*/
140 ''')
141 bsv_file.write(p.pinmux)
142 bsv_file.write('''
143 /*============================================================*/
144 ''')
145 # ====================================================================
146 # ================= interface definitions for each method =============#
147 bsv_file.write('''
148 interface mux_lines = interface MuxSelectionLines
149 ''')
150 for cell in p.muxed_cells:
151 bsv_file.write(mux_interface.ifacedef(cell[0],
152 int(math.log(len(cell) - 1, 2))))
153 bsv_file.write('''
154 endinterface;
155 interface peripheral_side = interface PeripheralSide
156 ''')
157 for i in range(0, p.N_IO):
158 bsv_file.write(io_interface.ifacedef(i))
159 ifaces.ifacedef(bsv_file)
160 bsv_file.write(footer)
161 print("BSV file successfully generated: bsv_src/pinmux.bsv")
162 # ======================================================================
163
164 with open('bsv_src/PinTop.bsv', 'w') as bsv_file:
165 bsv_file.write(copyright+'''
166 package PinTop;
167 import pinmux::*;
168 interface Ifc_PintTop;
169 method ActionValue#(Bool) write(Bit#({0}) addr, Bit#({1}) data);
170 method Tuple2#(Bool,Bit#({1})) read(Bit#({0}) addr);
171 interface PeripheralSide peripheral_side;
172 endinterface
173
174 module mkPinTop(Ifc_PintTop);
175 // instantiate the pin-mux module here
176 Ifc_pinmux pinmux <-mkpinmux;
177
178 // declare the registers which will be used to mux the IOs
179 '''.format(p.ADDR_WIDTH, p.DATA_WIDTH))
180
181 for cell in p.muxed_cells:
182 bsv_file.write('''
183 Reg#(Bit#({0})) rg_muxio_{1} <-mkReg(0);'''.format(
184 int(math.log(len(cell) - 1, 2)), cell[0]))
185
186 bsv_file.write('''
187 // rule to connect the registers to the selection lines of the
188 // pin-mux module
189 rule connect_selection_registers;''')
190
191 for cell in p.muxed_cells:
192 bsv_file.write('''
193 pinmux.mux_lines.cell{0}_mux(rg_muxio_{0});'''.format(cell[0]))
194
195 bsv_file.write('''
196 endrule
197 // method definitions for the write user interface
198 method ActionValue#(Bool) write(Bit#({2}) addr, Bit#({3}) data);
199 Bool err=False;
200 case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
201 p.ADDR_WIDTH, p.DATA_WIDTH))
202 index = 0
203 for cell in p.muxed_cells:
204 bsv_file.write('''
205 {0}: rg_muxio_{1}<=truncate(data);'''.format(index, cell[0]))
206 index = index + 1
207
208 bsv_file.write('''
209 default: err=True;
210 endcase
211 return err;
212 endmethod''')
213
214 bsv_file.write('''
215 // method definitions for the read user interface
216 method Tuple2#(Bool,Bit#({3})) read(Bit#({2}) addr);
217 Bool err=False;
218 Bit#(32) data=0;
219 case (addr[{0}:{1}])'''.format(p.upper_offset, p.lower_offset,
220 p.ADDR_WIDTH, p.DATA_WIDTH))
221 index = 0
222 for cell in p.muxed_cells:
223 bsv_file.write('''
224 {0}: data=zeroExtend(rg_muxio_{1});'''.format(index, cell[0]))
225 index = index + 1
226
227 bsv_file.write('''
228 default:err=True;
229 endcase
230 return tuple2(err,data);
231 endmethod
232 interface peripheral_side=pinmux.peripheral_side;
233 endmodule
234 endpackage
235 ''')
236
237 # ######## Generate bus transactors ################
238 with open('bsv_src/bus.bsv', 'w') as bsv_file:
239 bsv_file.write(axi4_lite.format(p.ADDR_WIDTH, p.DATA_WIDTH))
240 # ##################################################