src/proto/inst.proto

   1 // Copyright (c) 2014,2017 ARM Limited
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   3 //
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   6 // property including but not limited to intellectual property relating
   7 // to a hardware implementation of the functionality of the software
   8 // licensed hereunder.  You may use the software subject to the license
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  11 // modified or unmodified, in source code or in binary form.
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  13 // Redistribution and use in source and binary forms, with or without
  14 // modification, are permitted provided that the following conditions are
  15 // met: redistributions of source code must retain the above copyright
  16 // notice, this list of conditions and the following disclaimer;
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  22 // this software without specific prior written permission.
  23 //
  24 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  25 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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  34 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35 //
  36 // Authors: Ali Saidi
  37
  38 syntax = "proto2";
  39
  40 // Put all the generated messages in a namespace
  41 package ProtoMessage;
  42
  43 // Packet header with the identifier describing what object captured
  44 // the trace, the version of this file format, and the tick frequency
  45 // for all the packet time stamps.
  46 message InstHeader {
  47   required string obj_id = 1;
  48   required uint32 ver = 2 [default = 0];
  49   required uint64 tick_freq = 3;
  50   required bool has_mem = 4;
  51 }
  52
  53 message Inst {
  54   required uint64 pc = 1;
  55   required fixed32 inst = 2;
  56   optional uint32 nodeid = 3;
  57   optional uint32 cpuid = 4;
  58   optional fixed64 tick = 5;
  59
  60   enum InstType {
  61     None = 0;
  62     IntAlu = 1;
  63     IntMul = 2;
  64     IntDiv = 3;
  65     FloatAdd = 4;
  66     FloatCmp = 5;
  67     FloatCvt = 6;
  68     FloatMult = 7;
  69     FloatDiv = 8;
  70     FloatSqrt = 9;
  71     SIMDIntAdd = 10;
  72     SIMDIntAddAcc = 11;
  73     SIMDIntAlu = 12;
  74     SIMDIntCmp = 13;
  75     SIMDIntCvt = 14;
  76     SIMDMisc = 15;
  77     SIMDIntMult = 16;
  78     SIMDIntMultAcc = 17;
  79     SIMDIntShift = 18;
  80     SIMDIntShiftAcc = 19;
  81     SIMDSqrt = 20;
  82     SIMDFloatAdd = 21;
  83     SIMDFloatAlu = 22;
  84     SIMDFloatCmp = 23;
  85     SIMDFloatCvt = 24;
  86     SIMDFloatDiv = 25;
  87     SIMDFloatMisc = 26;
  88     SIMDFloatMult = 27;
  89     SIMDFloatMultAdd = 28;
  90     SIMDFloatSqrt = 29;
  91     MemRead = 30;
  92     MemWrite = 31;
  93     IprAccess = 32;
  94     InstPrefetch = 33;
  95   }
  96
  97   optional InstType type = 6; // add, mul, fp add, load, store, simd add, …
  98   optional uint32 inst_flags = 7; // execution mode information
  99
 100   // If the operation does one or more memory accesses
 101   message MemAccess {
 102       required uint64 addr = 1;
 103       required uint32 size = 2;
 104       optional uint32 mem_flags = 3;
 105   }
 106   repeated MemAccess mem_access = 8;
 107 }
 108