Merge zizzer:/bk/newmem
[gem5.git] / src / python / SConscript
1 # -*- mode:python -*-
2
3 # Copyright (c) 2004-2005 The Regents of The University of Michigan
4 # All rights reserved.
5 #
6 # Redistribution and use in source and binary forms, with or without
7 # modification, are permitted provided that the following conditions are
8 # met: redistributions of source code must retain the above copyright
9 # notice, this list of conditions and the following disclaimer;
10 # redistributions in binary form must reproduce the above copyright
11 # notice, this list of conditions and the following disclaimer in the
12 # documentation and/or other materials provided with the distribution;
13 # neither the name of the copyright holders nor the names of its
14 # contributors may be used to endorse or promote products derived from
15 # this software without specific prior written permission.
16 #
17 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 #
29 # Authors: Steve Reinhardt
30 # Nathan Binkert
31
32 import os
33 Import('*')
34
35 Source('swig/init.cc')
36 Source('swig/pyevent.cc')
37 Source('swig/pyobject.cc')
38
39 PySource('m5', 'm5/__init__.py')
40 PySource('m5', 'm5/SimObject.py')
41 PySource('m5', 'm5/attrdict.py')
42 PySource('m5', 'm5/convert.py')
43 PySource('m5', 'm5/event.py')
44 PySource('m5', 'm5/main.py')
45 PySource('m5', 'm5/multidict.py')
46 PySource('m5', 'm5/params.py')
47 PySource('m5', 'm5/proxy.py')
48 PySource('m5', 'm5/smartdict.py')
49 PySource('m5', 'm5/stats.py')
50 PySource('m5', 'm5/ticks.py')
51 PySource('m5', 'm5/util.py')
52
53 PySource('m5', os.path.join(env['ROOT'], 'util/pbs/jobfile.py'))
54
55 SwigSource('m5.internal', 'swig/core.i')
56 SwigSource('m5.internal', 'swig/debug.i')
57 SwigSource('m5.internal', 'swig/event.i')
58 SwigSource('m5.internal', 'swig/random.i')
59 SwigSource('m5.internal', 'swig/sim_object.i')
60 SwigSource('m5.internal', 'swig/stats.i')
61 SwigSource('m5.internal', 'swig/trace.i')
62 PySource('m5.internal', 'm5/internal/__init__.py')
63
64 SimObject('m5/objects/AlphaConsole.py')
65 SimObject('m5/objects/AlphaTLB.py')
66 SimObject('m5/objects/BadDevice.py')
67 SimObject('m5/objects/BaseCPU.py')
68 SimObject('m5/objects/BaseCache.py')
69 SimObject('m5/objects/BaseHier.py')
70 SimObject('m5/objects/BaseMem.py')
71 SimObject('m5/objects/BaseMemory.py')
72 SimObject('m5/objects/BranchPred.py')
73 SimObject('m5/objects/Bridge.py')
74 SimObject('m5/objects/Bus.py')
75 SimObject('m5/objects/Checker.py')
76 SimObject('m5/objects/CoherenceProtocol.py')
77 SimObject('m5/objects/DRAMMemory.py')
78 SimObject('m5/objects/Device.py')
79 SimObject('m5/objects/DiskImage.py')
80 SimObject('m5/objects/Ethernet.py')
81 SimObject('m5/objects/FUPool.py')
82 SimObject('m5/objects/FastCPU.py')
83 #SimObject('m5/objects/FreebsdSystem.py')
84 SimObject('m5/objects/FullCPU.py')
85 SimObject('m5/objects/FuncUnit.py')
86 SimObject('m5/objects/FuncUnitConfig.py')
87 SimObject('m5/objects/FunctionalMemory.py')
88 SimObject('m5/objects/HierParams.py')
89 SimObject('m5/objects/Ide.py')
90 SimObject('m5/objects/IntrControl.py')
91 SimObject('m5/objects/LinuxSystem.py')
92 SimObject('m5/objects/MainMemory.py')
93 SimObject('m5/objects/MemObject.py')
94 SimObject('m5/objects/MemTest.py')
95 SimObject('m5/objects/MemoryController.py')
96 SimObject('m5/objects/O3CPU.py')
97 SimObject('m5/objects/OzoneCPU.py')
98 SimObject('m5/objects/Pci.py')
99 SimObject('m5/objects/PhysicalMemory.py')
100 SimObject('m5/objects/PipeTrace.py')
101 SimObject('m5/objects/Platform.py')
102 SimObject('m5/objects/Process.py')
103 SimObject('m5/objects/Repl.py')
104 SimObject('m5/objects/Root.py')
105 SimObject('m5/objects/Sampler.py')
106 SimObject('m5/objects/Scsi.py')
107 SimObject('m5/objects/SimConsole.py')
108 SimObject('m5/objects/SimpleCPU.py')
109 SimObject('m5/objects/SimpleDisk.py')
110 #SimObject('m5/objects/SimpleOzoneCPU.py')
111 SimObject('m5/objects/SparcTLB.py')
112 SimObject('m5/objects/System.py')
113 SimObject('m5/objects/T1000.py')
114 #SimObject('m5/objects/Tru64System.py')
115 SimObject('m5/objects/Tsunami.py')
116 SimObject('m5/objects/Uart.py')
117
118 if env['ALPHA_TLASER']:
119 SimObject('m5/objects/DmaEngine.py')
120 SimObject('m5/objects/Turbolaser.py')