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HEAD
Merge vm1.(none):/home/stever/bk/newmem-head
[gem5.git]
/
src
/
python
/
m5
/
objects
/
AlphaTLB.py
1
from
m5
.
SimObject
import
SimObject
2
from
m5
.
params
import
*
3
class
AlphaTLB
(
SimObject
):
4
type
=
'AlphaTLB'
5
abstract
=
True
6
size
=
Param
.
Int
(
"TLB size"
)
7
8
class
AlphaDTB
(
AlphaTLB
):
9
type
=
'AlphaDTB'
10
size
=
64
11
12
class
AlphaITB
(
AlphaTLB
):
13
type
=
'AlphaITB'
14
size
=
48