1 from m5
.SimObject
import SimObject
2 from m5
.params
import *
4 from m5
import build_env
5 from AlphaTLB
import AlphaDTB
, AlphaITB
6 from SparcTLB
import SparcDTB
, SparcITB
10 class BaseCPU(SimObject
):
14 system
= Param
.System(Parent
.any
, "system object")
15 cpu_id
= Param
.Int("CPU identifier")
17 if build_env
['FULL_SYSTEM']:
18 do_quiesce
= Param
.Bool(True, "enable quiesce instructions")
19 do_checkpoint_insts
= Param
.Bool(True,
20 "enable checkpoint pseudo instructions")
21 do_statistics_insts
= Param
.Bool(True,
22 "enable statistics pseudo instructions")
24 if build_env
['TARGET_ISA'] == 'sparc':
25 dtb
= Param
.SparcDTB(SparcDTB(), "Data TLB")
26 itb
= Param
.SparcITB(SparcITB(), "Instruction TLB")
27 elif build_env
['TARGET_ISA'] == 'alpha':
28 dtb
= Param
.AlphaDTB(AlphaDTB(), "Data TLB")
29 itb
= Param
.AlphaITB(AlphaITB(), "Instruction TLB")
31 print "Unknown architecture, can't pick TLBs"
34 workload
= VectorParam
.Process("processes to run")
36 max_insts_all_threads
= Param
.Counter(0,
37 "terminate when all threads have reached this inst count")
38 max_insts_any_thread
= Param
.Counter(0,
39 "terminate when any thread reaches this inst count")
40 max_loads_all_threads
= Param
.Counter(0,
41 "terminate when all threads have reached this load count")
42 max_loads_any_thread
= Param
.Counter(0,
43 "terminate when any thread reaches this load count")
44 progress_interval
= Param
.Tick(0,
45 "interval to print out the progress message")
47 defer_registration
= Param
.Bool(False,
48 "defer registration with system (for sampling)")
50 clock
= Param
.Clock('1t', "clock speed")
51 phase
= Param
.Latency('0ns', "clock phase")
55 def connectMemPorts(self
, bus
):
56 for p
in self
._mem
_ports
:
57 exec('self.%s = bus.port' % p
)
59 def addPrivateSplitL1Caches(self
, ic
, dc
):
60 assert(len(self
._mem
_ports
) == 2)
63 self
.icache_port
= ic
.cpu_side
64 self
.dcache_port
= dc
.cpu_side
65 self
._mem
_ports
= ['icache.mem_side', 'dcache.mem_side']
67 def addTwoLevelCacheHierarchy(self
, ic
, dc
, l2c
):
68 self
.addPrivateSplitL1Caches(ic
, dc
)
70 self
.connectMemPorts(self
.toL2Bus
)
72 self
.l2cache
.cpu_side
= self
.toL2Bus
.port
73 self
._mem
_ports
= ['l2cache.mem_side']