src/python/m5/objects/BaseCPU.py

   1 from m5.SimObject import SimObject
   2 from m5.params import *
   3 from m5.proxy import *
   4 from m5 import build_env
   5 from AlphaTLB import AlphaDTB, AlphaITB
   6 from SparcTLB import SparcDTB, SparcITB
   7 from Bus import Bus
   8 import sys
   9
  10 class BaseCPU(SimObject):
  11     type = 'BaseCPU'
  12     abstract = True
  13
  14     system = Param.System(Parent.any, "system object")
  15     cpu_id = Param.Int("CPU identifier")
  16
  17     if build_env['FULL_SYSTEM']:
  18         do_quiesce = Param.Bool(True, "enable quiesce instructions")
  19         do_checkpoint_insts = Param.Bool(True,
  20             "enable checkpoint pseudo instructions")
  21         do_statistics_insts = Param.Bool(True,
  22             "enable statistics pseudo instructions")
  23
  24         if build_env['TARGET_ISA'] == 'sparc':
  25             dtb = Param.SparcDTB(SparcDTB(), "Data TLB")
  26             itb = Param.SparcITB(SparcITB(), "Instruction TLB")
  27         elif build_env['TARGET_ISA'] == 'alpha':
  28             dtb = Param.AlphaDTB(AlphaDTB(), "Data TLB")
  29             itb = Param.AlphaITB(AlphaITB(), "Instruction TLB")
  30         else:
  31             print "Unknown architecture, can't pick TLBs"
  32             sys.exit(1)
  33     else:
  34         workload = VectorParam.Process("processes to run")
  35
  36     max_insts_all_threads = Param.Counter(0,
  37         "terminate when all threads have reached this inst count")
  38     max_insts_any_thread = Param.Counter(0,
  39         "terminate when any thread reaches this inst count")
  40     max_loads_all_threads = Param.Counter(0,
  41         "terminate when all threads have reached this load count")
  42     max_loads_any_thread = Param.Counter(0,
  43         "terminate when any thread reaches this load count")
  44     progress_interval = Param.Tick(0,
  45         "interval to print out the progress message")
  46
  47     defer_registration = Param.Bool(False,
  48         "defer registration with system (for sampling)")
  49
  50     clock = Param.Clock('1t', "clock speed")
  51     phase = Param.Latency('0ns', "clock phase")
  52
  53     _mem_ports = []
  54
  55     def connectMemPorts(self, bus):
  56         for p in self._mem_ports:
  57             exec('self.%s = bus.port' % p)
  58
  59     def addPrivateSplitL1Caches(self, ic, dc):
  60         assert(len(self._mem_ports) == 2)
  61         self.icache = ic
  62         self.dcache = dc
  63         self.icache_port = ic.cpu_side
  64         self.dcache_port = dc.cpu_side
  65         self._mem_ports = ['icache.mem_side', 'dcache.mem_side']
  66
  67     def addTwoLevelCacheHierarchy(self, ic, dc, l2c):
  68         self.addPrivateSplitL1Caches(ic, dc)
  69         self.toL2Bus = Bus()
  70         self.connectMemPorts(self.toL2Bus)
  71         self.l2cache = l2c
  72         self.l2cache.cpu_side = self.toL2Bus.port
  73         self._mem_ports = ['l2cache.mem_side']