src/python/m5/objects/BaseCache.py

   1 from m5.params import *
   2 from MemObject import MemObject
   3
   4 class Prefetch(Enum): vals = ['none', 'tagged', 'stride', 'ghb']
   5
   6 class BaseCache(MemObject):
   7     type = 'BaseCache'
   8     adaptive_compression = Param.Bool(False,
   9         "Use an adaptive compression scheme")
  10     assoc = Param.Int("associativity")
  11     block_size = Param.Int("block size in bytes")
  12     latency = Param.Int("Latency")
  13     compressed_bus = Param.Bool(False,
  14         "This cache connects to a compressed memory")
  15     compression_latency = Param.Latency('0ns',
  16         "Latency in cycles of compression algorithm")
  17     hash_delay = Param.Int(1, "time in cycles of hash access")
  18     lifo = Param.Bool(False,
  19         "whether this NIC partition should use LIFO repl. policy")
  20     max_miss_count = Param.Counter(0,
  21         "number of misses to handle before calling exit")
  22     mshrs = Param.Int("number of MSHRs (max outstanding requests)")
  23     prioritizeRequests = Param.Bool(False,
  24         "always service demand misses first")
  25     protocol = Param.CoherenceProtocol(NULL, "coherence protocol to use")
  26     repl = Param.Repl(NULL, "replacement policy")
  27     size = Param.MemorySize("capacity in bytes")
  28     split = Param.Bool(False, "whether or not this cache is split")
  29     split_size = Param.Int(0,
  30         "How many ways of the cache belong to CPU/LRU partition")
  31     store_compressed = Param.Bool(False,
  32         "Store compressed data in the cache")
  33     subblock_size = Param.Int(0,
  34         "Size of subblock in IIC used for compression")
  35     tgts_per_mshr = Param.Int("max number of accesses per MSHR")
  36     trace_addr = Param.Addr(0, "address to trace")
  37     two_queue = Param.Bool(False,
  38         "whether the lifo should have two queue replacement")
  39     write_buffers = Param.Int(8, "number of write buffers")
  40     prefetch_miss = Param.Bool(False,
  41          "wheter you are using the hardware prefetcher from Miss stream")
  42     prefetch_access = Param.Bool(False,
  43          "wheter you are using the hardware prefetcher from Access stream")
  44     prefetcher_size = Param.Int(100,
  45          "Number of entries in the harware prefetch queue")
  46     prefetch_past_page = Param.Bool(False,
  47          "Allow prefetches to cross virtual page boundaries")
  48     prefetch_serial_squash = Param.Bool(False,
  49          "Squash prefetches with a later time on a subsequent miss")
  50     prefetch_degree = Param.Int(1,
  51          "Degree of the prefetch depth")
  52     prefetch_latency = Param.Tick(10,
  53          "Latency of the prefetcher")
  54     prefetch_policy = Param.Prefetch('none',
  55          "Type of prefetcher to use")
  56     prefetch_cache_check_push = Param.Bool(True,
  57          "Check if in cash on push or pop of prefetch queue")
  58     prefetch_use_cpu_id = Param.Bool(True,
  59          "Use the CPU ID to seperate calculations of prefetches")
  60     prefetch_data_accesses_only = Param.Bool(False,
  61          "Only prefetch on data not on instruction accesses")
  62     hit_latency = Param.Int(1,"Hit Latency of the cache")
  63     cpu_side = Port("Port on side closer to CPU")
  64     mem_side = Port("Port on side closer to MEM")