1 from m5
.SimObject
import SimObject
2 from m5
.params
import *
4 from m5
import build_env
5 from Device
import DmaDevice
6 from Pci
import PciDevice
, PciConfigData
8 class EtherInt(SimObject
):
11 peer
= Param
.EtherInt(NULL
, "peer interface")
13 class EtherLink(SimObject
):
15 int1
= Param
.EtherInt("interface 1")
16 int2
= Param
.EtherInt("interface 2")
17 delay
= Param
.Latency('0us', "packet transmit delay")
18 delay_var
= Param
.Latency('0ns', "packet transmit delay variability")
19 speed
= Param
.NetworkBandwidth('1Gbps', "link speed")
20 dump
= Param
.EtherDump(NULL
, "dump object")
22 class EtherBus(SimObject
):
24 loopback
= Param
.Bool(True, "send packet back to the sending interface")
25 dump
= Param
.EtherDump(NULL
, "dump object")
26 speed
= Param
.NetworkBandwidth('100Mbps', "bus speed in bits per second")
28 class EtherTap(EtherInt
):
30 bufsz
= Param
.Int(10000, "tap buffer size")
31 dump
= Param
.EtherDump(NULL
, "dump object")
32 port
= Param
.UInt16(3500, "tap port")
34 class EtherDump(SimObject
):
36 file = Param
.String("dump file")
37 maxlen
= Param
.Int(96, "max portion of packet data to dump")
39 if build_env
['ALPHA_TLASER']:
41 class EtherDev(DmaDevice
):
43 hardware_address
= Param
.EthernetAddr(NextEthernetAddr
,
44 "Ethernet Hardware Address")
46 dma_data_free
= Param
.Bool(False, "DMA of Data is free")
47 dma_desc_free
= Param
.Bool(False, "DMA of Descriptors is free")
48 dma_read_delay
= Param
.Latency('0us', "fixed delay for dma reads")
49 dma_read_factor
= Param
.Latency('0us', "multiplier for dma reads")
50 dma_write_delay
= Param
.Latency('0us', "fixed delay for dma writes")
51 dma_write_factor
= Param
.Latency('0us', "multiplier for dma writes")
52 dma_no_allocate
= Param
.Bool(True, "Should we allocate cache on read")
54 rx_filter
= Param
.Bool(True, "Enable Receive Filter")
55 rx_delay
= Param
.Latency('1us', "Receive Delay")
56 tx_delay
= Param
.Latency('1us', "Transmit Delay")
58 intr_delay
= Param
.Latency('0us', "Interrupt Delay")
59 payload_bus
= Param
.Bus(NULL
, "The IO Bus to attach to for payload")
60 physmem
= Param
.PhysicalMemory(Parent
.any
, "Physical Memory")
61 tlaser
= Param
.Turbolaser(Parent
.any
, "Turbolaser")
63 class EtherDevInt(EtherInt
):
65 device
= Param
.EtherDev("Ethernet device of this interface")
68 class IGbE(PciDevice
):
70 hardware_address
= Param
.String("Ethernet Hardware Address")
71 use_flow_control
= Param
.Bool(False, "Should we use xon/xoff flow contorl (UNIMPLMENTD)")
72 rx_fifo_size
= Param
.MemorySize('384kB', "Size of the rx FIFO")
73 tx_fifo_size
= Param
.MemorySize('384kB', "Size of the tx FIFO")
74 rx_desc_cache_size
= Param
.Int(64, "Number of enteries in the rx descriptor cache")
75 tx_desc_cache_size
= Param
.Int(64, "Number of enteries in the rx descriptor cache")
76 clock
= Param
.Clock('500MHz', "Clock speed of the device")
79 class IGbEPciData(PciConfigData
):
83 SubsystemVendorID
= 0x8086
100 class IGbEInt(EtherInt
):
102 device
= Param
.IGbE("Ethernet device of this interface")
106 class EtherDevBase(PciDevice
):
107 hardware_address
= Param
.EthernetAddr(NextEthernetAddr
,
108 "Ethernet Hardware Address")
110 clock
= Param
.Clock('0ns', "State machine processor frequency")
112 dma_read_delay
= Param
.Latency('0us', "fixed delay for dma reads")
113 dma_read_factor
= Param
.Latency('0us', "multiplier for dma reads")
114 dma_write_delay
= Param
.Latency('0us', "fixed delay for dma writes")
115 dma_write_factor
= Param
.Latency('0us', "multiplier for dma writes")
117 rx_delay
= Param
.Latency('1us', "Receive Delay")
118 tx_delay
= Param
.Latency('1us', "Transmit Delay")
119 rx_fifo_size
= Param
.MemorySize('512kB', "max size of rx fifo")
120 tx_fifo_size
= Param
.MemorySize('512kB', "max size of tx fifo")
122 rx_filter
= Param
.Bool(True, "Enable Receive Filter")
123 intr_delay
= Param
.Latency('10us', "Interrupt propagation delay")
124 rx_thread
= Param
.Bool(False, "dedicated kernel thread for transmit")
125 tx_thread
= Param
.Bool(False, "dedicated kernel threads for receive")
126 rss
= Param
.Bool(False, "Receive Side Scaling")
128 class NSGigEPciData(PciConfigData
):
141 MaximumLatency
= 0x34
148 class NSGigE(EtherDevBase
):
151 dma_data_free
= Param
.Bool(False, "DMA of Data is free")
152 dma_desc_free
= Param
.Bool(False, "DMA of Descriptors is free")
153 dma_no_allocate
= Param
.Bool(True, "Should we allocate cache on read")
155 configdata
= NSGigEPciData()
158 class NSGigEInt(EtherInt
):
160 device
= Param
.NSGigE("Ethernet device of this interface")
162 class SinicPciData(PciConfigData
):
175 MaximumLatency
= 0x34
181 class Sinic(EtherDevBase
):
184 rx_max_copy
= Param
.MemorySize('1514B', "rx max copy")
185 tx_max_copy
= Param
.MemorySize('16kB', "tx max copy")
186 rx_max_intr
= Param
.UInt32(10, "max rx packets per interrupt")
187 rx_fifo_threshold
= Param
.MemorySize('384kB', "rx fifo high threshold")
188 rx_fifo_low_mark
= Param
.MemorySize('128kB', "rx fifo low threshold")
189 tx_fifo_high_mark
= Param
.MemorySize('384kB', "tx fifo high threshold")
190 tx_fifo_threshold
= Param
.MemorySize('128kB', "tx fifo low threshold")
191 virtual_count
= Param
.UInt32(1, "Virtualized SINIC")
192 zero_copy
= Param
.Bool(False, "Zero copy receive")
193 delay_copy
= Param
.Bool(False, "Delayed copy transmit")
194 virtual_addr
= Param
.Bool(False, "Virtual addressing")
196 configdata
= SinicPciData()
198 class SinicInt(EtherInt
):
200 device
= Param
.Sinic("Ethernet device of this interface")