Override addPrivateSplitL1Caches function in order to automatically set the tgts_per_...
[gem5.git] / src / python / m5 / objects / Pci.py
1 from m5.SimObject import SimObject
2 from m5.params import *
3 from m5.proxy import *
4 from Device import BasicPioDevice, DmaDevice, PioDevice
5
6 class PciConfigData(SimObject):
7 type = 'PciConfigData'
8 VendorID = Param.UInt16("Vendor ID")
9 DeviceID = Param.UInt16("Device ID")
10 Command = Param.UInt16(0, "Command")
11 Status = Param.UInt16(0, "Status")
12 Revision = Param.UInt8(0, "Device")
13 ProgIF = Param.UInt8(0, "Programming Interface")
14 SubClassCode = Param.UInt8(0, "Sub-Class Code")
15 ClassCode = Param.UInt8(0, "Class Code")
16 CacheLineSize = Param.UInt8(0, "System Cacheline Size")
17 LatencyTimer = Param.UInt8(0, "PCI Latency Timer")
18 HeaderType = Param.UInt8(0, "PCI Header Type")
19 BIST = Param.UInt8(0, "Built In Self Test")
20
21 BAR0 = Param.UInt32(0x00, "Base Address Register 0")
22 BAR1 = Param.UInt32(0x00, "Base Address Register 1")
23 BAR2 = Param.UInt32(0x00, "Base Address Register 2")
24 BAR3 = Param.UInt32(0x00, "Base Address Register 3")
25 BAR4 = Param.UInt32(0x00, "Base Address Register 4")
26 BAR5 = Param.UInt32(0x00, "Base Address Register 5")
27 BAR0Size = Param.MemorySize32('0B', "Base Address Register 0 Size")
28 BAR1Size = Param.MemorySize32('0B', "Base Address Register 1 Size")
29 BAR2Size = Param.MemorySize32('0B', "Base Address Register 2 Size")
30 BAR3Size = Param.MemorySize32('0B', "Base Address Register 3 Size")
31 BAR4Size = Param.MemorySize32('0B', "Base Address Register 4 Size")
32 BAR5Size = Param.MemorySize32('0B', "Base Address Register 5 Size")
33
34 CardbusCIS = Param.UInt32(0x00, "Cardbus Card Information Structure")
35 SubsystemID = Param.UInt16(0x00, "Subsystem ID")
36 SubsystemVendorID = Param.UInt16(0x00, "Subsystem Vendor ID")
37 ExpansionROM = Param.UInt32(0x00, "Expansion ROM Base Address")
38 InterruptLine = Param.UInt8(0x00, "Interrupt Line")
39 InterruptPin = Param.UInt8(0x00, "Interrupt Pin")
40 MaximumLatency = Param.UInt8(0x00, "Maximum Latency")
41 MinimumGrant = Param.UInt8(0x00, "Minimum Grant")
42
43 class PciConfigAll(PioDevice):
44 type = 'PciConfigAll'
45 pio_latency = Param.Tick(1, "Programmed IO latency in simticks")
46 bus = Param.UInt8(0x00, "PCI bus to act as config space for")
47 size = Param.MemorySize32('16MB', "Size of config space")
48
49
50 class PciDevice(DmaDevice):
51 type = 'PciDevice'
52 abstract = True
53 config = Port(Self.pio.peerObj.port, "PCI configuration space port")
54 pci_bus = Param.Int("PCI bus")
55 pci_dev = Param.Int("PCI device number")
56 pci_func = Param.Int("PCI function code")
57 pio_latency = Param.Latency('1ns', "Programmed IO latency in simticks")
58 configdata = Param.PciConfigData(Parent.any, "PCI Config data")
59 config_latency = Param.Latency('20ns', "Config read or write latency")