src/python/m5/objects/PhysicalMemory.py

   1 from m5.params import *
   2 from m5.proxy import *
   3 from MemObject import *
   4
   5 class PhysicalMemory(MemObject):
   6     type = 'PhysicalMemory'
   7     port = Port("the access port")
   8     functional = Port("Functional Access Port")
   9     range = Param.AddrRange(AddrRange('128MB'), "Device Address")
  10     file = Param.String('', "memory mapped file")
  11     latency = Param.Latency(Parent.clock, "latency of an access")
  12
  13 class DRAMMemory(PhysicalMemory):
  14     type = 'DRAMMemory'
  15     # Many of these should be observed from the configuration
  16     cpu_ratio = Param.Int(5,"ratio between CPU speed and memory bus speed")
  17     mem_type = Param.String("SDRAM", "Type of DRAM (DRDRAM, SDRAM)")
  18     mem_actpolicy = Param.String("open", "Open/Close policy")
  19     memctrladdr_type = Param.String("interleaved", "Mapping interleaved or direct")
  20     bus_width = Param.Int(16, "")
  21     act_lat = Param.Int(2, "RAS to CAS delay")
  22     cas_lat = Param.Int(1, "CAS delay")
  23     war_lat = Param.Int(2, "write after read delay")
  24     pre_lat = Param.Int(2, "precharge delay")
  25     dpl_lat = Param.Int(2, "data in to precharge delay")
  26     trc_lat = Param.Int(6, "row cycle delay")
  27     num_banks = Param.Int(4, "Number of Banks")
  28     num_cpus = Param.Int(4, "Number of CPUs connected to DRAM")
  29