1 from m5
.params
import *
3 from MemObject
import *
5 class PhysicalMemory(MemObject
):
6 type = 'PhysicalMemory'
7 port
= Port("the access port")
8 functional
= Port("Functional Access Port")
9 range = Param
.AddrRange(AddrRange('128MB'), "Device Address")
10 file = Param
.String('', "memory mapped file")
11 latency
= Param
.Latency(Parent
.clock
, "latency of an access")
12 zero
= Param
.Bool(False, "zero initialize memory")
14 class DRAMMemory(PhysicalMemory
):
16 # Many of these should be observed from the configuration
17 cpu_ratio
= Param
.Int(5,"ratio between CPU speed and memory bus speed")
18 mem_type
= Param
.String("SDRAM", "Type of DRAM (DRDRAM, SDRAM)")
19 mem_actpolicy
= Param
.String("open", "Open/Close policy")
20 memctrladdr_type
= Param
.String("interleaved", "Mapping interleaved or direct")
21 bus_width
= Param
.Int(16, "")
22 act_lat
= Param
.Int(2, "RAS to CAS delay")
23 cas_lat
= Param
.Int(1, "CAS delay")
24 war_lat
= Param
.Int(2, "write after read delay")
25 pre_lat
= Param
.Int(2, "precharge delay")
26 dpl_lat
= Param
.Int(2, "data in to precharge delay")
27 trc_lat
= Param
.Int(6, "row cycle delay")
28 num_banks
= Param
.Int(4, "Number of Banks")
29 num_cpus
= Param
.Int(4, "Number of CPUs connected to DRAM")