ab4687f7f25a5162e58209385147393f27ac778d
1 # Copyright (c) 2012-2013 ARM Limited
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
6 # property including but not limited to intellectual property relating
7 # to a hardware implementation of the functionality of the software
8 # licensed hereunder. You may use the software subject to the license
9 # terms below provided that you ensure that this notice is replicated
10 # unmodified and in its entirety in all distributions of the software,
11 # modified or unmodified, in source code or in binary form.
13 # Redistribution and use in source and binary forms, with or without
14 # modification, are permitted provided that the following conditions are
15 # met: redistributions of source code must retain the above copyright
16 # notice, this list of conditions and the following disclaimer;
17 # redistributions in binary form must reproduce the above copyright
18 # notice, this list of conditions and the following disclaimer in the
19 # documentation and/or other materials provided with the distribution;
20 # neither the name of the copyright holders nor the names of its
21 # contributors may be used to endorse or promote products derived from
22 # this software without specific prior written permission.
24 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 # Authors: Andreas Hansson
39 #####################################################################
41 # System visualization using DOT
43 # While config.ini and config.json provide an almost complete listing
44 # of a system's components and connectivity, they lack a birds-eye
45 # view. The output generated by do_dot() is a DOT-based figure (as a
46 # pdf and an editable svg file) and its source dot code. Nodes are
47 # components, and edges represent the memory hierarchy: the edges are
48 # directed, from a master to slave. Initially all nodes are
49 # generated, and then all edges are added. do_dot should be called
50 # with the top-most SimObject (namely root but not necessarily), the
51 # output folder and the output dot source filename. From the given
52 # node, both processes (node and edge creation) is performed
53 # recursivly, traversing all children of the given root.
55 # pydot is required. When missing, no output will be generated.
57 #####################################################################
60 from m5
.SimObject
import isRoot
, isSimObjectVector
61 from m5
.params
import PortRef
62 from m5
.util
import warn
68 # need to create all nodes (components) before creating edges (memory channels)
69 def dot_create_nodes(simNode
, callgraph
):
74 full_path
= re
.sub('\.', '_', simNode
.path())
75 # add class name under the label
76 label
= "\"" + label
+ " \\n: " + simNode
.__class
__.__name
__ + "\""
78 # each component is a sub-graph (cluster)
79 cluster
= dot_create_cluster(simNode
, full_path
, label
)
81 # create nodes per port
82 for port_name
in simNode
._ports
.keys():
83 port
= simNode
._port
_refs
.get(port_name
, None)
85 full_port_name
= full_path
+ "_" + port_name
86 port_node
= dot_create_node(simNode
, full_port_name
, port_name
)
87 cluster
.add_node(port_node
)
91 for c
in simNode
._children
:
92 child
= simNode
._children
[c
]
93 if isSimObjectVector(child
):
95 dot_create_nodes(obj
, cluster
)
97 dot_create_nodes(child
, cluster
)
99 callgraph
.add_subgraph(cluster
)
101 # create all edges according to memory hierarchy
102 def dot_create_edges(simNode
, callgraph
):
103 for port_name
in simNode
._ports
.keys():
104 port
= simNode
._port
_refs
.get(port_name
, None)
106 full_path
= re
.sub('\.', '_', simNode
.path())
107 full_port_name
= full_path
+ "_" + port_name
108 port_node
= dot_create_node(simNode
, full_port_name
, port_name
)
110 if isinstance(port
, PortRef
):
111 dot_add_edge(simNode
, callgraph
, full_port_name
, port
)
113 for p
in port
.elements
:
114 dot_add_edge(simNode
, callgraph
, full_port_name
, p
)
116 # recurse to children
117 if simNode
._children
:
118 for c
in simNode
._children
:
119 child
= simNode
._children
[c
]
120 if isSimObjectVector(child
):
122 dot_create_edges(obj
, callgraph
)
124 dot_create_edges(child
, callgraph
)
126 def dot_add_edge(simNode
, callgraph
, full_port_name
, peerPort
):
127 if peerPort
.role
== "MASTER":
128 peer_port_name
= re
.sub('\.', '_', peerPort
.peer
.simobj
.path() \
129 + "." + peerPort
.peer
.name
)
130 callgraph
.add_edge(pydot
.Edge(full_port_name
, peer_port_name
))
132 def dot_create_cluster(simNode
, full_path
, label
):
133 # get the parameter values of the node and use them as a tooltip
135 for param
in sorted(simNode
._params
.keys()):
136 value
= simNode
._values
.get(param
)
138 # parameter name = value in HTML friendly format
139 ini_strings
.append(str(param
) + "=" +
140 simNode
._values
[param
].ini_str())
141 # join all the parameters with an HTML newline
142 tooltip
= " ".join(ini_strings
)
144 return pydot
.Cluster( \
148 tooltip
= "\"" + tooltip
+ "\"", \
149 style
= "\"rounded, filled\"", \
151 fillcolor
= dot_gen_colour(simNode
), \
152 fontname
= "Arial", \
154 fontcolor
= "#000000" \
157 def dot_create_node(simNode
, full_path
, label
):
162 style
= "\"rounded, filled\"", \
164 fillcolor
= dot_gen_colour(simNode
, True), \
165 fontname
= "Arial", \
167 fontcolor
= "#000000" \
170 # an enumerator for different kinds of node types, at the moment we
171 # discern the majority of node types, with the caches being the
181 # based on the sim object, determine the node type
182 def get_node_type(simNode
):
183 if isinstance(simNode
, m5
.objects
.System
):
185 # NULL ISA has no BaseCPU or PioDevice, so check if these names
186 # exists before using them
187 elif 'BaseCPU' in dir(m5
.objects
) and \
188 isinstance(simNode
, m5
.objects
.BaseCPU
):
190 elif 'PioDevice' in dir(m5
.objects
) and \
191 isinstance(simNode
, m5
.objects
.PioDevice
):
193 elif isinstance(simNode
, m5
.objects
.BaseBus
):
195 elif isinstance(simNode
, m5
.objects
.AbstractMemory
):
198 return NodeType
.OTHER
200 # based on the node type, determine the colour as an RGB tuple, the
201 # palette is rather arbitrary at this point (some coherent natural
202 # tones), and someone that feels artistic should probably have a look
203 def get_type_colour(nodeType
):
204 if nodeType
== NodeType
.SYS
:
205 return (228, 231, 235)
206 elif nodeType
== NodeType
.CPU
:
207 return (187, 198, 217)
208 elif nodeType
== NodeType
.BUS
:
209 return (111, 121, 140)
210 elif nodeType
== NodeType
.MEM
:
212 elif nodeType
== NodeType
.DEV
:
213 return (199, 167, 147)
214 elif nodeType
== NodeType
.OTHER
:
215 # use a relatively gray shade
216 return (186, 182, 174)
218 # generate colour for a node, either corresponding to a sim object or a
220 def dot_gen_colour(simNode
, isPort
= False):
221 # determine the type of the current node, and also its parent, if
222 # the node is not the same type as the parent then we use the base
223 # colour for its type
224 node_type
= get_node_type(simNode
)
226 parent_type
= get_node_type(simNode
._parent
)
228 parent_type
= NodeType
.OTHER
230 # if this node is the same type as the parent, then scale the
231 # colour based on the depth such that the deeper levels in the
232 # hierarchy get darker colours
233 if node_type
== parent_type
:
234 # start out with a depth of zero
236 parent
= simNode
._parent
237 # find the closes parent that is not the same type
238 while parent
and get_node_type(parent
) == parent_type
:
240 parent
= parent
._parent
241 node_colour
= get_type_colour(parent_type
)
242 # slightly arbitrary, but assume that the depth is less than
244 r
, g
, b
= map(lambda x
: x
* max(1 - depth
/ 7.0, 0.3), node_colour
)
246 node_colour
= get_type_colour(node_type
)
247 r
, g
, b
= node_colour
249 # if we are colouring a port, then make it a slightly darker shade
250 # than the node that encapsulates it, once again use a magic constant
252 r
, g
, b
= map(lambda x
: 0.8 * x
, (r
, g
, b
))
254 return dot_rgb_to_html(r
, g
, b
)
256 def dot_rgb_to_html(r
, g
, b
):
257 return "#%.2x%.2x%.2x" % (r
, g
, b
)
259 def do_dot(root
, outdir
, dotFilename
):
262 # * use ranksep > 1.0 for for vertical separation between nodes
263 # especially useful if you need to annotate edges using e.g. visio
264 # which accepts svg format
265 # * no need for hoizontal separation as nothing moves horizonally
266 callgraph
= pydot
.Dot(graph_type
='digraph', ranksep
='1.3')
267 dot_create_nodes(root
, callgraph
)
268 dot_create_edges(root
, callgraph
)
269 dot_filename
= os
.path
.join(outdir
, dotFilename
)
270 callgraph
.write(dot_filename
)
272 # dot crashes if the figure is extremely wide.
273 # So avoid terminating simulation unnecessarily
274 callgraph
.write_svg(dot_filename
+ ".svg")
275 callgraph
.write_pdf(dot_filename
+ ".pdf")
277 warn("failed to generate dot output from %s", dot_filename
)