1 from nmigen
.compat
.sim
import run_simulation
2 from nmigen
.cli
import verilog
, rtlil
3 from nmigen
import Module
, Signal
, Elaboratable
, Array
, Cat
4 from nmutil
.latch
import SRLatch
7 class DepCell(Elaboratable
):
8 """ implements 11.4.7 mitch alsup dependence cell, p27
9 adjusted to be clock-sync'd on rising edge only.
10 mitch design (as does 6600) requires alternating rising/falling clock
14 self
.reg_i
= Signal(reset_less
=True) # reg bit in (top)
15 self
.issue_i
= Signal(reset_less
=True) # Issue in (top)
16 self
.go_i
= Signal(reset_less
=True) # Go read/write in (left)
18 # for Register File Select Lines (vertical)
19 self
.rsel_o
= Signal(reset_less
=True) # reg sel (bottom)
20 # for Function Unit "forward progress" (horizontal)
21 self
.fwd_o
= Signal(reset_less
=True) # FU forard progress (right)
23 def elaborate(self
, platform
):
25 m
.submodules
.l
= l
= SRLatch(sync
=False) # async latch
27 # record current version of q in a sync'd register
28 cq
= Signal() # resets to 0
29 m
.d
.sync
+= cq
.eq(l
.q
)
31 # reset on go HI, set on dest and issue
32 m
.d
.comb
+= l
.s
.eq(self
.issue_i
& self
.reg_i
)
33 m
.d
.comb
+= l
.r
.eq(self
.go_i
)
35 # Function Unit "Forward Progress".
36 m
.d
.comb
+= self
.fwd_o
.eq((l
.q
) & self
.reg_i
& ~self
.issue_i
)
38 # Register Select. Activated on go read/write and *current* latch set
39 m
.d
.comb
+= self
.rsel_o
.eq((cq | l
.q
) & self
.go_i
)
54 class DependenceCell(Elaboratable
):
55 """ implements 11.4.7 mitch alsup dependence cell, p27
59 self
.dest_i
= Signal(reset_less
=True) # Dest in (top)
60 self
.src1_i
= Signal(reset_less
=True) # oper1 in (top)
61 self
.src2_i
= Signal(reset_less
=True) # oper2 in (top)
62 self
.issue_i
= Signal(reset_less
=True) # Issue in (top)
64 self
.go_wr_i
= Signal(reset_less
=True) # Go Write in (left)
65 self
.go_rd_i
= Signal(reset_less
=True) # Go Read in (left)
67 # for Register File Select Lines (vertical)
68 self
.dest_rsel_o
= Signal(reset_less
=True) # dest reg sel (bottom)
69 self
.src1_rsel_o
= Signal(reset_less
=True) # src1 reg sel (bottom)
70 self
.src2_rsel_o
= Signal(reset_less
=True) # src2 reg sel (bottom)
72 # for Function Unit "forward progress" (horizontal)
73 self
.dest_fwd_o
= Signal(reset_less
=True) # dest FU fw (right)
74 self
.src1_fwd_o
= Signal(reset_less
=True) # src1 FU fw (right)
75 self
.src2_fwd_o
= Signal(reset_less
=True) # src2 FU fw (right)
77 def elaborate(self
, platform
):
79 m
.submodules
.dest_c
= dest_c
= DepCell()
80 m
.submodules
.src1_c
= src1_c
= DepCell()
81 m
.submodules
.src2_c
= src2_c
= DepCell()
84 for c
in [dest_c
, src1_c
, src2_c
]:
85 m
.d
.comb
+= c
.issue_i
.eq(self
.issue_i
)
87 # connect go_rd / go_wr (dest->wr, src->rd)
88 m
.d
.comb
+= dest_c
.go_i
.eq(self
.go_wr_i
)
89 m
.d
.comb
+= src1_c
.go_i
.eq(self
.go_rd_i
)
90 m
.d
.comb
+= src2_c
.go_i
.eq(self
.go_rd_i
)
92 # connect input reg bit (unary)
93 for c
, reg
in [(dest_c
, self
.dest_i
),
94 (src1_c
, self
.src1_i
),
95 (src2_c
, self
.src2_i
)]:
96 m
.d
.comb
+= c
.reg_i
.eq(reg
)
98 # connect fwd / reg-sel outputs
99 for c
, fwd
, rsel
in [(dest_c
, self
.dest_fwd_o
, self
.dest_rsel_o
),
100 (src1_c
, self
.src1_fwd_o
, self
.src1_rsel_o
),
101 (src2_c
, self
.src2_fwd_o
, self
.src2_rsel_o
)]:
102 m
.d
.comb
+= fwd
.eq(c
.fwd_o
)
103 m
.d
.comb
+= rsel
.eq(c
.rsel_o
)
114 yield self
.dest_rsel_o
115 yield self
.src1_rsel_o
116 yield self
.src2_rsel_o
117 yield self
.dest_fwd_o
118 yield self
.src1_fwd_o
119 yield self
.src2_fwd_o
125 class DependencyRow(Elaboratable
):
126 def __init__(self
, n_reg_col
):
127 self
.n_reg_col
= n_reg_col
130 # fields all match DependencyCell precisely
132 self
.dest_i
= Signal(n_reg_col
, reset_less
=True)
133 self
.src1_i
= Signal(n_reg_col
, reset_less
=True)
134 self
.src2_i
= Signal(n_reg_col
, reset_less
=True)
136 self
.issue_i
= Signal(reset_less
=True)
137 self
.go_wr_i
= Signal(reset_less
=True)
138 self
.go_rd_i
= Signal(reset_less
=True)
140 self
.dest_rsel_o
= Signal(n_reg_col
, reset_less
=True)
141 self
.src1_rsel_o
= Signal(n_reg_col
, reset_less
=True)
142 self
.src2_rsel_o
= Signal(n_reg_col
, reset_less
=True)
144 self
.dest_fwd_o
= Signal(n_reg_col
, reset_less
=True)
145 self
.src1_fwd_o
= Signal(n_reg_col
, reset_less
=True)
146 self
.src2_fwd_o
= Signal(n_reg_col
, reset_less
=True)
148 def elaborate(self
, platform
):
150 rcell
= Array(DependenceCell() for f
in range(self
.n_reg_col
))
151 for rn
in range(self
.n_reg_col
):
152 setattr(m
.submodules
, "dm_r%d" % rn
, rcell
[rn
])
155 # connect Dep dest/src to module dest/src
160 for rn
in range(self
.n_reg_col
):
162 # accumulate cell inputs dest/src1/src2
163 dest_i
.append(dc
.dest_i
)
164 src1_i
.append(dc
.src1_i
)
165 src2_i
.append(dc
.src2_i
)
166 # wire up inputs from module to row cell inputs (Cat is gooood)
167 m
.d
.comb
+= [Cat(*dest_i
).eq(self
.dest_i
),
168 Cat(*src1_i
).eq(self
.src1_i
),
169 Cat(*src2_i
).eq(self
.src2_i
),
173 # connect Dep issue_i/go_rd_i/go_wr_i to module issue_i/go_rd/go_wr
175 for rn
in range(self
.n_reg_col
):
177 m
.d
.comb
+= [dc
.go_rd_i
.eq(self
.go_rd_i
),
178 dc
.go_wr_i
.eq(self
.go_wr_i
),
179 dc
.issue_i
.eq(self
.issue_i
),
183 # connect Function Unit vector
188 for rn
in range(self
.n_reg_col
):
190 # accumulate cell fwd outputs for dest/src1/src2
191 dest_fwd_o
.append(dc
.dest_fwd_o
)
192 src1_fwd_o
.append(dc
.src1_fwd_o
)
193 src2_fwd_o
.append(dc
.src2_fwd_o
)
194 # connect cell fwd outputs to FU Vector Out [Cat is gooood]
195 m
.d
.comb
+= [self
.dest_fwd_o
.eq(Cat(*dest_fwd_o
)),
196 self
.src1_fwd_o
.eq(Cat(*src1_fwd_o
)),
197 self
.src2_fwd_o
.eq(Cat(*src2_fwd_o
))
201 # connect Reg Selection vector
206 for rn
in range(self
.n_reg_col
):
208 # accumulate cell reg-select outputs dest/src1/src2
209 dest_rsel_o
.append(dc
.dest_rsel_o
)
210 src1_rsel_o
.append(dc
.src1_rsel_o
)
211 src2_rsel_o
.append(dc
.src2_rsel_o
)
212 # connect cell reg-select outputs to Reg Vector Out
213 m
.d
.comb
+= self
.dest_rsel_o
.eq(Cat(*dest_rsel_o
))
214 m
.d
.comb
+= self
.src1_rsel_o
.eq(Cat(*src1_rsel_o
))
215 m
.d
.comb
+= self
.src2_rsel_o
.eq(Cat(*src2_rsel_o
))
226 yield self
.dest_rsel_o
227 yield self
.src1_rsel_o
228 yield self
.src2_rsel_o
229 yield self
.dest_fwd_o
230 yield self
.src1_fwd_o
231 yield self
.src2_fwd_o
238 yield dut
.dest_i
.eq(1)
239 yield dut
.issue_i
.eq(1)
241 yield dut
.issue_i
.eq(0)
243 yield dut
.src1_i
.eq(1)
244 yield dut
.issue_i
.eq(1)
248 yield dut
.issue_i
.eq(0)
250 yield dut
.go_rd_i
.eq(1)
252 yield dut
.go_rd_i
.eq(0)
254 yield dut
.go_wr_i
.eq(1)
256 yield dut
.go_wr_i
.eq(0)
260 dut
= DependencyRow(4)
261 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
262 with
open("test_drow.il", "w") as f
:
265 dut
= DependenceCell()
266 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
267 with
open("test_dcell.il", "w") as f
:
270 run_simulation(dut
, dcell_sim(dut
), vcd_name
='test_dcell.vcd')
272 if __name__
== '__main__':