1 from nmigen
.compat
.sim
import run_simulation
2 from nmigen
.cli
import verilog
, rtlil
3 from nmigen
import Module
, Signal
, Cat
, Array
, Const
, Elaboratable
4 from nmigen
.lib
.coding
import Decoder
6 from nmutil
.latch
import SRLatch
, latchregister
8 from scoreboard
.shadow
import Shadow
11 class FnUnit(Elaboratable
):
12 """ implements 11.4.8 function unit, p31
13 also implements optional shadowing 11.5.1, p55
15 shadowing can be used for branches as well as exceptions (interrupts),
16 load/store hold (exceptions again), and vector-element predication
17 (once the predicate is known, which it may not be at instruction issue)
21 * :wid: register file width
22 * :shadow_wid: number of shadow/fail/good/go_die sets
23 * :n_dests: number of destination regfile(s) (index: rfile_sel_i)
24 * :wr_pend: if true, writable observes the g_wr_pend_i vector
25 otherwise observes g_rd_pend_i
29 * dest_i / src1_i / src2_i are in *binary*, whereas...
30 * ...g_rd_pend_i / g_wr_pend_i and rd_pend_o / wr_pend_o are UNARY
31 * req_rel_i (request release) is the direct equivalent of pipeline
32 "output valid" (valid_o)
33 * recover is a local python variable (actually go_die_o)
34 * when shadow_wid = 0, recover and shadown are Consts (i.e. do nothing)
35 * wr_pend is set False for the majority of uses: however for
36 use in a STORE Function Unit it is set to True
38 def __init__(self
, wid
, shadow_wid
=0, n_dests
=1, wr_pend
=False):
40 self
.n_dests
= n_dests
41 self
.shadow_wid
= shadow_wid
42 self
.wr_pend
= wr_pend
46 self
.rfile_sel_i
= Signal(max=n_dests
, reset_less
=True)
48 self
.rfile_sel_i
= Const(0) # no selection. gets Array[0]
49 self
.dest_i
= Signal(max=wid
, reset_less
=True) # Dest R# in (top)
50 self
.src1_i
= Signal(max=wid
, reset_less
=True) # oper1 R# in (top)
51 self
.src2_i
= Signal(max=wid
, reset_less
=True) # oper2 R# in (top)
52 self
.issue_i
= Signal(reset_less
=True) # Issue in (top)
54 self
.go_wr_i
= Signal(reset_less
=True) # Go Write in (left)
55 self
.go_rd_i
= Signal(reset_less
=True) # Go Read in (left)
56 self
.req_rel_i
= Signal(reset_less
=True) # request release (left)
58 self
.g_xx_pend_i
= Array(Signal(wid
, reset_less
=True, name
="g_pend_i") \
59 for i
in range(n_dests
)) # global rd (right)
60 self
.g_wr_pend_i
= Signal(wid
, reset_less
=True) # global wr (right)
63 self
.shadow_i
= Signal(shadow_wid
, reset_less
=True)
64 self
.s_fail_i
= Signal(shadow_wid
, reset_less
=True)
65 self
.s_good_i
= Signal(shadow_wid
, reset_less
=True)
66 self
.go_die_o
= Signal(reset_less
=True)
69 self
.readable_o
= Signal(reset_less
=True) # Readable out (right)
70 self
.writable_o
= Array(Signal(reset_less
=True, name
="writable_o") \
71 for i
in range(n_dests
)) # writable out (right)
72 self
.busy_o
= Signal(reset_less
=True) # busy out (left)
74 self
.src1_pend_o
= Signal(wid
, reset_less
=True) # src1 pending
75 self
.src2_pend_o
= Signal(wid
, reset_less
=True) # src1 pending
76 self
.rd_pend_o
= Signal(wid
, reset_less
=True) # rd pending (right)
77 self
.xx_pend_o
= Array(Signal(wid
, reset_less
=True, name
="pend_o") \
78 for i
in range(n_dests
))# wr pending (right)
80 def elaborate(self
, platform
):
82 m
.submodules
.rd_l
= rd_l
= SRLatch(sync
=False)
83 m
.submodules
.wr_l
= wr_l
= SRLatch(sync
=False)
84 m
.submodules
.dest_d
= dest_d
= Decoder(self
.reg_width
)
85 m
.submodules
.src1_d
= src1_d
= Decoder(self
.reg_width
)
86 m
.submodules
.src2_d
= src2_d
= Decoder(self
.reg_width
)
88 # shadow / recover (optional: shadow_wid > 0)
89 m
.submodules
.shadow
= shadow
= Shadow(self
.shadow_wid
)
91 m
.d
.comb
+= shadow
.issue_i
.eq(self
.issue_i
)
92 m
.d
.comb
+= shadow
.s_fail_i
.eq(self
.s_fail_i
)
93 m
.d
.comb
+= shadow
.s_good_i
.eq(self
.s_good_i
)
94 m
.d
.comb
+= shadow
.shadow_i
.eq(self
.shadow_i
)
95 shadown
= shadow
.shadown_o
96 recover
= shadow
.go_die_o
99 xx_pend_o
= self
.xx_pend_o
[self
.rfile_sel_i
]
100 writable_o
= self
.writable_o
[self
.rfile_sel_i
]
101 g_pend_i
= self
.g_xx_pend_i
[self
.rfile_sel_i
]
103 for i
in range(self
.n_dests
):
104 m
.d
.comb
+= self
.xx_pend_o
[i
].eq(0) # initialise all array
105 m
.d
.comb
+= self
.writable_o
[i
].eq(0) # to zero
106 m
.d
.comb
+= self
.readable_o
.eq(0) # to zero
108 # go_wr latch: reset on go_wr HI, set on issue
109 m
.d
.comb
+= wr_l
.s
.eq(self
.issue_i
)
110 m
.d
.comb
+= wr_l
.r
.eq(self
.go_wr_i | recover
)
112 # src1 latch: reset on go_rd HI, set on issue
113 m
.d
.comb
+= rd_l
.s
.eq(self
.issue_i
)
114 m
.d
.comb
+= rd_l
.r
.eq(self
.go_rd_i | recover
)
116 # latch/registers for dest / src1 / src2
117 dest_r
= Signal(max=self
.reg_width
, reset_less
=True)
118 src1_r
= Signal(max=self
.reg_width
, reset_less
=True)
119 src2_r
= Signal(max=self
.reg_width
, reset_less
=True)
120 # XXX latch based on *issue* rather than !latch (as in book)
121 latchregister(m
, self
.dest_i
, dest_r
, self
.issue_i
) #wr_l.qn)
122 latchregister(m
, self
.src1_i
, src1_r
, self
.issue_i
) #wr_l.qn)
123 latchregister(m
, self
.src2_i
, src2_r
, self
.issue_i
) #wr_l.qn)
125 # dest decoder (use dest reg as input): write-pending out
126 m
.d
.comb
+= dest_d
.i
.eq(dest_r
)
127 m
.d
.comb
+= dest_d
.n
.eq(wr_l
.qn
) # decode is inverted
128 m
.d
.comb
+= self
.busy_o
.eq(wr_l
.q
) # busy if set
129 m
.d
.comb
+= xx_pend_o
.eq(dest_d
.o
)
131 # src1/src2 decoder (use src1/2 regs as input): read-pending out
132 m
.d
.comb
+= src1_d
.i
.eq(src1_r
)
133 m
.d
.comb
+= src1_d
.n
.eq(rd_l
.qn
) # decode is inverted
134 m
.d
.comb
+= src2_d
.i
.eq(src2_r
)
135 m
.d
.comb
+= src2_d
.n
.eq(rd_l
.qn
) # decode is inverted
136 m
.d
.comb
+= self
.src1_pend_o
.eq(src1_d
.o
)
137 m
.d
.comb
+= self
.src2_pend_o
.eq(src2_d
.o
)
138 m
.d
.comb
+= self
.rd_pend_o
.eq(src1_d
.o | src2_d
.o
)
140 # readable output signal
141 g_rd
= Signal(self
.reg_width
, reset_less
=True)
142 ro
= Signal(reset_less
=True)
143 m
.d
.comb
+= g_rd
.eq(~self
.g_wr_pend_i
& self
.rd_pend_o
)
144 m
.d
.comb
+= ro
.eq(~g_rd
.bool())
145 m
.d
.comb
+= self
.readable_o
.eq(ro
)
147 # writable output signal
148 g_wr_v
= Signal(self
.reg_width
, reset_less
=True)
149 g_wr
= Signal(reset_less
=True)
150 wo
= Signal(reset_less
=True)
151 m
.d
.comb
+= g_wr_v
.eq(g_pend_i
& xx_pend_o
)
152 m
.d
.comb
+= g_wr
.eq(~g_wr_v
.bool())
153 m
.d
.comb
+= wo
.eq(g_wr
& rd_l
.qn
& self
.req_rel_i
& shadown
)
154 m
.d
.comb
+= writable_o
.eq(wo
)
166 yield from self
.g_xx_pend_i
167 yield self
.g_wr_pend_i
168 yield self
.readable_o
169 yield from self
.writable_o
171 yield from self
.xx_pend_o
176 ############# ###############
178 # --- renamed / redirected from base class --- #
180 # --- below are convenience classes which match the names --- #
181 # --- of the various mitch alsup book chapter gate diagrams --- #
183 ############# ###############
186 class IntFnUnit(FnUnit
):
187 def __init__(self
, wid
, shadow_wid
=0):
188 FnUnit
.__init
__(self
, wid
, shadow_wid
)
189 self
.int_rd_pend_o
= self
.rd_pend_o
190 self
.int_wr_pend_o
= self
.xx_pend_o
[0]
191 self
.g_int_wr_pend_i
= self
.g_wr_pend_i
192 self
.g_int_rd_pend_i
= self
.g_xx_pend_i
[0]
193 self
.int_readable_o
= self
.readable_o
194 self
.int_writable_o
= self
.writable_o
[0]
196 self
.int_rd_pend_o
.name
= "int_rd_pend_o"
197 self
.int_wr_pend_o
.name
= "int_wr_pend_o"
198 self
.g_int_rd_pend_i
.name
= "g_int_rd_pend_i"
199 self
.g_int_wr_pend_i
.name
= "g_int_wr_pend_i"
200 self
.int_readable_o
.name
= "int_readable_o"
201 self
.int_writable_o
.name
= "int_writable_o"
204 class FPFnUnit(FnUnit
):
205 def __init__(self
, wid
, shadow_wid
=0):
206 FnUnit
.__init
__(self
, wid
, shadow_wid
)
207 self
.fp_rd_pend_o
= self
.rd_pend_o
208 self
.fp_wr_pend_o
= self
.xx_pend_o
[0]
209 self
.g_fp_wr_pend_i
= self
.g_wr_pend_i
210 self
.g_fp_rd_pend_i
= self
.g_xx_pend_i
[0]
211 self
.fp_writable_o
= self
.writable_o
[0]
212 self
.fp_readable_o
= self
.readable_o
214 self
.fp_rd_pend_o
.name
= "fp_rd_pend_o"
215 self
.fp_wr_pend_o
.name
= "fp_wr_pend_o"
216 self
.g_fp_rd_pend_i
.name
= "g_fp_rd_pend_i"
217 self
.g_fp_wr_pend_i
.name
= "g_fp_wr_pend_i"
218 self
.fp_writable_o
.name
= "fp_writable_o"
219 self
.fp_readable_o
.name
= "fp_readable_o"
222 class LDFnUnit(FnUnit
):
223 """ number of dest selectors: 2. assumes len(int_regfile) == len(fp_regfile)
224 * when rfile_sel_i == 0, int_wr_pend_o is set
225 * when rfile_sel_i == 1, fp_wr_pend_o is set
227 def __init__(self
, wid
, shadow_wid
=0):
228 FnUnit
.__init
__(self
, wid
, shadow_wid
, n_dests
=2)
229 self
.int_rd_pend_o
= self
.rd_pend_o
230 self
.int_wr_pend_o
= self
.xx_pend_o
[0]
231 self
.fp_wr_pend_o
= self
.xx_pend_o
[1]
232 self
.g_int_wr_pend_i
= self
.g_wr_pend_i
233 self
.g_int_rd_pend_i
= self
.g_xx_pend_i
[0]
234 self
.g_fp_rd_pend_i
= self
.g_xx_pend_i
[1]
235 self
.int_readable_o
= self
.readable_o
236 self
.int_writable_o
= self
.writable_o
[0]
237 self
.fp_writable_o
= self
.writable_o
[1]
239 self
.int_rd_pend_o
.name
= "int_rd_pend_o"
240 self
.int_wr_pend_o
.name
= "int_wr_pend_o"
241 self
.fp_wr_pend_o
.name
= "fp_wr_pend_o"
242 self
.g_int_wr_pend_i
.name
= "g_int_wr_pend_i"
243 self
.g_int_rd_pend_i
.name
= "g_int_rd_pend_i"
244 self
.g_fp_rd_pend_i
.name
= "g_fp_rd_pend_i"
245 self
.int_readable_o
.name
= "int_readable_o"
246 self
.int_writable_o
.name
= "int_writable_o"
247 self
.fp_writable_o
.name
= "fp_writable_o"
250 class STFnUnit(FnUnit
):
251 """ number of dest selectors: 2. assumes len(int_regfile) == len(fp_regfile)
252 * wr_pend=False indicates to observe global fp write pending
253 * when rfile_sel_i == 0, int_wr_pend_o is set
254 * when rfile_sel_i == 1, fp_wr_pend_o is set
257 def __init__(self
, wid
, shadow_wid
=0):
258 FnUnit
.__init
__(self
, wid
, shadow_wid
, n_dests
=2, wr_pend
=True)
259 self
.int_rd_pend_o
= self
.rd_pend_o
# 1st int read-pending vector
260 self
.int2_rd_pend_o
= self
.xx_pend_o
[0] # 2nd int read-pending vector
261 self
.fp_rd_pend_o
= self
.xx_pend_o
[1] # 1x FP read-pending vector
262 # yes overwrite FnUnit base class g_wr_pend_i vector
263 self
.g_int_wr_pend_i
= self
.g_wr_pend_i
= self
.g_xx_pend_i
[0]
264 self
.g_fp_wr_pend_i
= self
.g_xx_pend_i
[1]
265 self
.int_readable_o
= self
.readable_o
266 self
.int_writable_o
= self
.writable_o
[0]
267 self
.fp_writable_o
= self
.writable_o
[1]
269 self
.int_rd_pend_o
.name
= "int_rd_pend_o"
270 self
.int2_rd_pend_o
.name
= "int2_rd_pend_o"
271 self
.fp_rd_pend_o
.name
= "fp_rd_pend_o"
272 self
.g_int_wr_pend_i
.name
= "g_int_wr_pend_i"
273 self
.g_fp_wr_pend_i
.name
= "g_fp_wr_pend_i"
274 self
.int_readable_o
.name
= "int_readable_o"
275 self
.int_writable_o
.name
= "int_writable_o"
276 self
.fp_writable_o
.name
= "fp_writable_o"
280 def int_fn_unit_sim(dut
):
281 yield dut
.dest_i
.eq(1)
282 yield dut
.issue_i
.eq(1)
284 yield dut
.issue_i
.eq(0)
286 yield dut
.src1_i
.eq(1)
287 yield dut
.issue_i
.eq(1)
291 yield dut
.issue_i
.eq(0)
293 yield dut
.go_rd_i
.eq(1)
295 yield dut
.go_rd_i
.eq(0)
297 yield dut
.go_wr_i
.eq(1)
299 yield dut
.go_wr_i
.eq(0)
302 def test_int_fn_unit():
303 dut
= FnUnit(32, 2, 2)
304 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
305 with
open("test_fn_unit.il", "w") as f
:
308 dut
= LDFnUnit(32, 2)
309 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
310 with
open("test_ld_fn_unit.il", "w") as f
:
313 dut
= STFnUnit(32, 0)
314 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
315 with
open("test_st_fn_unit.il", "w") as f
:
318 run_simulation(dut
, int_fn_unit_sim(dut
), vcd_name
='test_fn_unit.vcd')
320 if __name__
== '__main__':