1 from nmigen
.compat
.sim
import run_simulation
2 from nmigen
.cli
import verilog
, rtlil
3 from nmigen
import Module
, Signal
, Elaboratable
4 from nmutil
.latch
import SRLatch
7 class FUDependenceCell(Elaboratable
):
8 """ implements 11.4.7 mitch alsup dependence cell, p27
12 self
.rd_pend_i
= Signal(reset_less
=True) # read pending in (left)
13 self
.wr_pend_i
= Signal(reset_less
=True) # write pending in (left)
14 self
.issue_i
= Signal(reset_less
=True) # Issue in (top)
16 self
.go_write_i
= Signal(reset_less
=True) # Go Write in (left)
17 self
.go_read_i
= Signal(reset_less
=True) # Go Read in (left)
19 # outputs (latched rd/wr pend)
20 self
.rd_pend_o
= Signal(reset_less
=True) # read pending out (right)
21 self
.wr_pend_o
= Signal(reset_less
=True) # write pending out (right)
23 def elaborate(self
, platform
):
25 m
.submodules
.rd_l
= rd_l
= SRLatch()
26 m
.submodules
.wr_l
= wr_l
= SRLatch()
28 # write latch: reset on go_write HI, set on write pending and issue
29 m
.d
.comb
+= wr_l
.s
.eq(self
.issue_i
& self
.wr_pend_i
)
30 m
.d
.comb
+= wr_l
.r
.eq(self
.go_write_i
)
32 # read latch: reset on go_read HI, set on read pending and issue
33 m
.d
.comb
+= rd_l
.s
.eq(self
.issue_i
& self
.rd_pend_i
)
34 m
.d
.comb
+= rd_l
.r
.eq(self
.go_read_i
)
36 # Read/Write Pending Latches (read out horizontally)
37 m
.d
.comb
+= self
.wr_pend_o
.eq(wr_l
.qn
)
38 m
.d
.comb
+= self
.rd_pend_o
.eq(rd_l
.qn
)
56 yield dut
.dest_i
.eq(1)
57 yield dut
.issue_i
.eq(1)
59 yield dut
.issue_i
.eq(0)
61 yield dut
.src1_i
.eq(1)
62 yield dut
.issue_i
.eq(1)
64 yield dut
.issue_i
.eq(0)
66 yield dut
.go_read_i
.eq(1)
68 yield dut
.go_read_i
.eq(0)
70 yield dut
.go_write_i
.eq(1)
72 yield dut
.go_write_i
.eq(0)
76 dut
= FUDependenceCell()
77 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
78 with
open("test_fu_dcell.il", "w") as f
:
81 run_simulation(dut
, dcell_sim(dut
), vcd_name
='test_fu_dcell.vcd')
83 if __name__
== '__main__':