333d5b1b8a6e2f6d00cfd71129fd5f06b76bb3a3
1 from nmigen
.compat
.sim
import run_simulation
2 from nmigen
.cli
import verilog
, rtlil
3 from nmigen
import Module
, Signal
, Cat
, Elaboratable
6 class PriorityPicker(Elaboratable
):
7 """ implements a priority-picker. input: N bits, output: N bits
9 def __init__(self
, wid
):
12 self
.i
= Signal(wid
, reset_less
=True)
13 self
.o
= Signal(wid
, reset_less
=True)
15 def elaborate(self
, platform
):
19 for i
in range(0, self
.wid
):
20 t
= Signal(reset_less
= True)
23 m
.d
.comb
+= t
.eq(self
.i
[0])
25 m
.d
.comb
+= t
.eq((~res
[-2]) & self
.i
[i
])
28 # we like Cat(*xxx). turn lists into concatenated bits
29 m
.d
.comb
+= self
.o
.eq(Cat(*res
))
41 class GroupPicker(Elaboratable
):
42 """ implements 10.5 mitch alsup group picker, p27
44 def __init__(self
, wid
):
47 self
.readable_i
= Signal(wid
, reset_less
=True) # readable in (top)
48 self
.writable_i
= Signal(wid
, reset_less
=True) # writable in (top)
49 self
.req_rel_i
= Signal(wid
, reset_less
=True) # release request in (top)
52 self
.go_rd_o
= Signal(wid
, reset_less
=True) # go read (bottom)
53 self
.go_wr_o
= Signal(wid
, reset_less
=True) # go write (bottom)
55 def elaborate(self
, platform
):
58 m
.submodules
.rpick
= rpick
= PriorityPicker(self
.gp_wid
)
59 m
.submodules
.wpick
= wpick
= PriorityPicker(self
.gp_wid
)
61 # combine release (output ready signal) with writeable
62 m
.d
.comb
+= wpick
.i
.eq(self
.writable_i
& self
.req_rel_i
)
63 m
.d
.comb
+= self
.go_wr_o
.eq(wpick
.o
)
65 m
.d
.comb
+= rpick
.i
.eq(self
.readable_i
)
66 m
.d
.comb
+= self
.go_rd_o
.eq(rpick
.o
)
81 def grp_pick_sim(dut
):
82 yield dut
.dest_i
.eq(1)
83 yield dut
.issue_i
.eq(1)
85 yield dut
.issue_i
.eq(0)
87 yield dut
.src1_i
.eq(1)
88 yield dut
.issue_i
.eq(1)
92 yield dut
.issue_i
.eq(0)
94 yield dut
.go_rd_i
.eq(1)
96 yield dut
.go_rd_i
.eq(0)
98 yield dut
.go_wr_i
.eq(1)
100 yield dut
.go_wr_i
.eq(0)
105 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
106 with
open("test_grp_pick.il", "w") as f
:
109 run_simulation(dut
, grp_pick_sim(dut
), vcd_name
='test_grp_pick.vcd')
111 if __name__
== '__main__':