1 from nmigen
.compat
.sim
import run_simulation
2 from nmigen
.cli
import verilog
, rtlil
3 from nmigen
import Module
, Signal
, Cat
, Array
, Const
, Repl
, Elaboratable
4 from nmigen
.lib
.coding
import Decoder
6 from scoreboard
.group_picker
import PriorityPicker
9 class RegDecode(Elaboratable
):
10 """ decodes registers into unary
14 * :wid: register file width
16 def __init__(self
, wid
):
20 self
.enable_i
= Signal(reset_less
=True) # enable decoders
21 self
.dest_i
= Signal(max=wid
, reset_less
=True) # Dest R# in
22 self
.src1_i
= Signal(max=wid
, reset_less
=True) # oper1 R# in
23 self
.src2_i
= Signal(max=wid
, reset_less
=True) # oper2 R# in
26 self
.dest_o
= Signal(wid
, reset_less
=True) # Dest unary out
27 self
.src1_o
= Signal(wid
, reset_less
=True) # oper1 unary out
28 self
.src2_o
= Signal(wid
, reset_less
=True) # oper2 unary out
30 def elaborate(self
, platform
):
32 m
.submodules
.dest_d
= dest_d
= Decoder(self
.reg_width
)
33 m
.submodules
.src1_d
= src1_d
= Decoder(self
.reg_width
)
34 m
.submodules
.src2_d
= src2_d
= Decoder(self
.reg_width
)
36 # dest decoder: write-pending
37 for d
, i
, o
in [(dest_d
, self
.dest_i
, self
.dest_o
),
38 (src1_d
, self
.src1_i
, self
.src1_o
),
39 (src2_d
, self
.src2_i
, self
.src2_o
)]:
41 m
.d
.comb
+= d
.n
.eq(~self
.enable_i
)
59 class IssueUnitGroup(Elaboratable
):
60 """ Manages a batch of Computation Units all of which can do the same task
62 A priority picker will allocate one instruction in this cycle based
63 on whether the others are busy.
65 insn_i indicates to this module that there is an instruction to be
66 issued which this group can handle
68 busy_i is a vector of signals that indicate, in this cycle, which
69 of the units are currently busy.
71 g_issue_o indicates whether it is "safe to proceed" i.e. whether
72 there is a unit here that can *be* issued an instruction
74 fn_issue_o indicates, out of the available (non-busy) units,
75 which one may be selected
77 def __init__(self
, n_insns
):
78 """ Set up inputs and outputs for the Group
82 * :n_insns: number of instructions in this issue unit.
84 self
.n_insns
= n_insns
87 self
.insn_i
= Signal(reset_less
=True, name
="insn_i")
88 self
.busy_i
= Signal(n_insns
, reset_less
=True, name
="busy_i")
91 self
.fn_issue_o
= Signal(n_insns
, reset_less
=True, name
="fn_issue_o")
92 self
.g_issue_o
= Signal(reset_less
=True)
94 def elaborate(self
, platform
):
100 m
.submodules
.pick
= pick
= PriorityPicker(self
.n_insns
)
103 allissue
= Signal(self
.n_insns
, reset_less
=True)
104 all1
= Const(-1, self
.n_insns
)
106 m
.d
.comb
+= allissue
.eq(Repl(self
.insn_i
, self
.n_insns
))
107 # Pick one (and only one) of the units to proceed in this cycle
108 m
.d
.comb
+= pick
.i
.eq(~self
.busy_i
& allissue
)
110 # "Safe to issue" condition is basically when all units are not busy
111 m
.d
.comb
+= self
.g_issue_o
.eq((self
.busy_i
!= all1
))
113 # Picker only raises one signal, therefore it's also the fn_issue
114 m
.d
.comb
+= self
.fn_issue_o
.eq(pick
.o
)
121 yield self
.fn_issue_o
128 class IssueUnit(Elaboratable
):
129 """ implements 11.4.14 issue unit, p50
133 * :wid: register file width
134 * :n_insns: number of instructions in this issue unit.
136 def __init__(self
, wid
, n_insns
):
138 self
.n_insns
= n_insns
141 self
.store_i
= Signal(reset_less
=True) # instruction is a store
142 self
.dest_i
= Signal(wid
, reset_less
=True) # Dest R in (unary)
144 self
.g_wr_pend_i
= Signal(wid
, reset_less
=True) # write pending vector
146 self
.insn_i
= Signal(n_insns
, reset_less
=True, name
="insn_i")
147 self
.busy_i
= Signal(n_insns
, reset_less
=True, name
="busy_i")
150 self
.fn_issue_o
= Signal(n_insns
, reset_less
=True, name
="fn_issue_o")
151 self
.g_issue_o
= Signal(reset_less
=True)
153 def elaborate(self
, platform
):
156 if self
.n_insns
== 0:
160 waw_stall
= Signal(reset_less
=True)
161 fu_stall
= Signal(reset_less
=True)
162 pend
= Signal(self
.reg_width
, reset_less
=True)
164 # dest decoder: write-pending
165 m
.d
.comb
+= pend
.eq(self
.dest_i
& self
.g_wr_pend_i
)
166 m
.d
.comb
+= waw_stall
.eq(pend
.bool() & (~self
.store_i
))
169 for i
in range(self
.n_insns
):
170 ib_l
.append(self
.insn_i
[i
] & self
.busy_i
[i
])
171 m
.d
.comb
+= fu_stall
.eq(Cat(*ib_l
).bool())
172 m
.d
.comb
+= self
.g_issue_o
.eq(~
(waw_stall | fu_stall
))
173 for i
in range(self
.n_insns
):
174 m
.d
.comb
+= self
.fn_issue_o
[i
].eq(self
.g_issue_o
& self
.insn_i
[i
])
183 yield self
.reg_enable_i
184 yield self
.g_wr_pend_i
185 yield from self
.insn_i
186 yield from self
.busy_i
187 yield from self
.fn_issue_o
194 class IntFPIssueUnit(Elaboratable
):
195 def __init__(self
, wid
, n_int_insns
, n_fp_insns
):
196 self
.i
= IssueUnit(wid
, n_int_insns
)
197 self
.f
= IssueUnit(wid
, n_fp_insns
)
198 self
.issue_o
= Signal(reset_less
=True)
201 self
.int_wr_pend_i
= self
.i
.g_wr_pend_i
202 self
.fp_wr_pend_i
= self
.f
.g_wr_pend_i
203 self
.int_wr_pend_i
.name
= 'int_wr_pend_i'
204 self
.fp_wr_pend_i
.name
= 'fp_wr_pend_i'
206 def elaborate(self
, platform
):
208 m
.submodules
.intissue
= self
.i
209 m
.submodules
.fpissue
= self
.f
211 m
.d
.comb
+= self
.issue_o
.eq(self
.i
.g_issue_o | self
.f
.g_issue_o
)
221 def issue_unit_sim(dut
):
222 yield dut
.dest_i
.eq(1)
223 yield dut
.issue_i
.eq(1)
225 yield dut
.issue_i
.eq(0)
227 yield dut
.src1_i
.eq(1)
228 yield dut
.issue_i
.eq(1)
232 yield dut
.issue_i
.eq(0)
234 yield dut
.go_rd_i
.eq(1)
236 yield dut
.go_rd_i
.eq(0)
238 yield dut
.go_wr_i
.eq(1)
240 yield dut
.go_wr_i
.eq(0)
243 def test_issue_unit():
244 dut
= IssueUnitGroup(3)
245 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
246 with
open("test_issue_unit_group.il", "w") as f
:
249 dut
= IssueUnit(32, 3)
250 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
251 with
open("test_issue_unit.il", "w") as f
:
254 dut
= IntFPIssueUnit(32, 3, 3)
255 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
256 with
open("test_intfp_issue_unit.il", "w") as f
:
259 run_simulation(dut
, issue_unit_sim(dut
), vcd_name
='test_issue_unit.vcd')
261 if __name__
== '__main__':