1 """ Mitch Alsup 6600-style LD/ST scoreboard Dependency Cell
4 * http://bugs.libre-riscv.org/show_bug.cgi?id=81
8 from nmigen
.compat
.sim
import run_simulation
9 from nmigen
.cli
import verilog
, rtlil
10 from nmigen
import Module
, Signal
, Elaboratable
11 from nmutil
.latch
import SRLatch
14 class LDSTDepCell(Elaboratable
):
15 """ implements 11.4.12 mitch alsup load/store dependence cell, p45
19 self
.load_i
= Signal(reset_less
=True) # load pending in (top)
20 self
.stor_i
= Signal(reset_less
=True) # store pending in (top)
21 self
.issue_i
= Signal(reset_less
=True) # Issue in (top)
23 self
.load_hit_i
= Signal(reset_less
=True) # load hit in (right)
24 self
.stwd_hit_i
= Signal(reset_less
=True) # store w/ data hit in (right)
26 # outputs (latched rd/wr pend)
27 self
.ld_hold_st_o
= Signal(reset_less
=True) # load holds st out (left)
28 self
.st_hold_ld_o
= Signal(reset_less
=True) # st holds load out (left)
30 def elaborate(self
, platform
):
32 m
.submodules
.war_l
= war_l
= SRLatch(sync
=False) # WriteAfterRead Latch
33 m
.submodules
.raw_l
= raw_l
= SRLatch(sync
=False) # ReadAfterWrite Latch
35 # issue & store & load - used for both WAR and RAW Setting
36 i_s_l
= Signal(reset_less
=True)
37 m
.d
.comb
+= i_s_l
.eq(self
.issue_i
& self
.stor_i
& self
.load_i
)
39 # write after read latch: loads block stores
40 m
.d
.comb
+= war_l
.s
.eq(i_s_l
)
41 m
.d
.comb
+= war_l
.r
.eq(self
.load_i
) # reset on LD
43 # read after write latch: stores block loads
44 m
.d
.comb
+= raw_l
.s
.eq(i_s_l
)
45 m
.d
.comb
+= raw_l
.r
.eq(self
.stor_i
) # reset on ST
47 # Hold results (read out horizontally, accumulate in OR fashion)
48 m
.d
.comb
+= self
.ld_hold_st_o
.eq(war_l
.qn
& self
.load_hit_i
)
49 m
.d
.comb
+= self
.st_hold_ld_o
.eq(raw_l
.qn
& self
.stwd_hit_i
)
59 yield self
.ld_hold_st_o
60 yield self
.st_hold_ld_o
67 yield dut
.dest_i
.eq(1)
68 yield dut
.issue_i
.eq(1)
70 yield dut
.issue_i
.eq(0)
72 yield dut
.src1_i
.eq(1)
73 yield dut
.issue_i
.eq(1)
75 yield dut
.issue_i
.eq(0)
77 yield dut
.go_read_i
.eq(1)
79 yield dut
.go_read_i
.eq(0)
81 yield dut
.go_write_i
.eq(1)
83 yield dut
.go_write_i
.eq(0)
88 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
89 with
open("test_ldst_dcell.il", "w") as f
:
92 run_simulation(dut
, dcell_sim(dut
), vcd_name
='test_ldst_dcell.vcd')
94 if __name__
== '__main__':