1 from nmigen
import Elaboratable
, Module
, Signal
, Cat
4 class MemFU_Pend(Elaboratable
):
5 """ these are allocated per-FU (horizontally),
6 and are of length reg_count
8 def __init__(self
, reg_count
):
9 self
.reg_count
= reg_count
10 self
.ld_fwd_i
= Signal(reg_count
, reset_less
=True)
11 self
.st_fwd_i
= Signal(reg_count
, reset_less
=True)
13 self
.reg_ld_pend_o
= Signal(reset_less
=True)
14 self
.reg_st_pend_o
= Signal(reset_less
=True)
16 def elaborate(self
, platform
):
18 m
.d
.comb
+= self
.reg_ld_pend_o
.eq(self
.ld_fwd_i
.bool())
19 m
.d
.comb
+= self
.reg_st_pend_o
.eq(self
.st_fwd_i
.bool())