94ceac7ec4c873e144092fd1d6eb3ed46922058c
1 """ testing of InstructionQ
4 from copy
import deepcopy
5 from random
import randint
6 from nmigen
.compat
.sim
import run_simulation
7 from nmigen
.cli
import verilog
, rtlil
9 from scoreboard
.instruction_q
import InstructionQ
10 from nmutil
.nmoperator
import eq
14 def __init__(self
, dut
, iq
, n_in
, n_out
):
23 while i
< len(self
.iq
):
24 sendlen
= randint(1, self
.n_in
)
26 sendlen
= min(len(self
.iq
) - i
, sendlen
)
27 print ("sendlen", len(self
.iq
)-i
, sendlen
)
28 for idx
in range(sendlen
):
29 instr
= self
.iq
[i
+idx
]
30 yield from eq(self
.dut
.data_i
[idx
], instr
)
31 di
= yield self
.dut
.data_i
[idx
]#.src1_i
32 print ("senddata %d %x" % ((i
+idx
), di
))
34 yield self
.dut
.p_add_i
.eq(sendlen
)
36 o_p_ready
= yield self
.dut
.p_ready_o
39 o_p_ready
= yield self
.dut
.p_ready_o
41 yield self
.dut
.p_add_i
.eq(0)
43 print ("send", len(self
.iq
), i
, sendlen
)
45 # wait random period of time before queueing another value
46 for j
in range(randint(0, 3)):
51 yield self
.dut
.p_add_i
.eq(0)
56 ## wait random period of time before queueing another value
57 #for i in range(randint(0, 3)):
60 #send_range = randint(0, 3)
64 # send = randint(0, send_range) != 0
71 while i
< len(self
.iq
):
72 rcvlen
= randint(1, self
.n_out
)
73 #print ("outreq", rcvlen)
74 yield self
.dut
.n_sub_i
.eq(rcvlen
)
75 n_sub_o
= yield self
.dut
.n_sub_o
76 print ("recv", n_sub_o
)
77 for j
in range(n_sub_o
):
78 r
= yield self
.dut
.data_o
[j
]#.src1_i
79 print ("recvdata %x %s" % (r
, repr(self
.iq
[i
+j
])))
80 assert r
== self
.oq
[i
+j
]
84 yield self
.dut
.n_sub_i
.eq(0)
91 def mk_insns(n_insns
, wid
, opwid
):
93 for i
in range(n_insns
):
94 op1
= randint(0, (1<<wid
)-1)
96 op2
= randint(0, (1<<wid
)-1)
97 dst
= randint(0, (1<<wid
)-1)
98 oper
= randint(0, (1<<opwid
)-1)
99 imm
= randint(0, (1<<wid
)-1)
100 res
.append({'oper_i': oper
, 'opim_i': opi
,
101 'imm_i': imm
, 'dest_i': dst
,
102 'src1_i': op1
, 'src2_i': op2
})
112 dut
= InstructionQ(wid
, opwid
, qlen
, n_in
, n_out
)
113 insns
= mk_insns(1000, wid
, opwid
)
115 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
116 with
open("test_iq.il", "w") as f
:
119 test
= IQSim(dut
, insns
, n_in
, n_out
)
121 run_simulation(dut
, [test
.rcv(), test
.send()
123 vcd_name
="test_iq.vcd")
125 if __name__
== '__main__':