src/sim/ClockDomain.py

   1 # Copyright (c) 2013-2014 ARM Limited
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  36 # Authors: Vasileios Spiliopoulos
  37 #          Akash Bagdia
  38 #          Stephan Diestelhorst
  39
  40 from m5.params import *
  41 from m5.SimObject import SimObject
  42 from m5.proxy import *
  43
  44 # Abstract clock domain
  45 class ClockDomain(SimObject):
  46     type = 'ClockDomain'
  47     cxx_header = "sim/clock_domain.hh"
  48     abstract = True
  49
  50 # Source clock domain with an actual clock, and a list of voltage and frequency
  51 # op points
  52 class SrcClockDomain(ClockDomain):
  53     type = 'SrcClockDomain'
  54     cxx_header = "sim/clock_domain.hh"
  55
  56     # Single clock frequency value, or list of frequencies for DVFS
  57     # Frequencies must be ordered in descending order
  58     # Note: Matching voltages should be defined in the voltage domain
  59     clock = VectorParam.Clock("Clock period")
  60
  61     # A source clock must be associated with a voltage domain
  62     voltage_domain = Param.VoltageDomain("Voltage domain")
  63
  64     # Domain ID is an identifier for the DVFS domain as understood by the
  65     # necessary control logic (either software or hardware). For example, in
  66     # case of software control via cpufreq framework the IDs should correspond
  67     # to the neccessary identifier in the device tree blob which is interpretted
  68     # by the device driver to communicate to the domain controller in hardware.
  69     domain_id = Param.Int32(-1, "domain id")
  70
  71     # Initial performance level from the list of available operation points
  72     # Defaults to maximum performance
  73     init_perf_level = Param.UInt32(0, "Initial performance level")
  74
  75 # Derived clock domain with a parent clock domain and a frequency
  76 # divider
  77 class DerivedClockDomain(ClockDomain):
  78     type = 'DerivedClockDomain'
  79     cxx_header = "sim/clock_domain.hh"
  80     clk_domain = Param.ClockDomain("Parent clock domain")
  81     clk_divider = Param.Unsigned(1, "Frequency divider")