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36 from m5
.SimObject
import SimObject
37 from m5
.params
import *
38 from m5
.proxy
import *
40 # Enumerate set of allowed power states that can be used by a clocked object.
41 # The list is kept generic to express a base minimal set.
43 # Undefined: Invalid state, no power state derived information is available.
44 # On: The logic block is actively running and consuming dynamic and leakage
45 # energy depending on the amount of processing required.
46 # Clk_gated: The clock circuity within the block is gated to save dynamic
47 # energy, the power supply to the block is still on and leakage
48 # energy is being consumed by the block.
49 # Sram_retention: The SRAMs within the logic blocks are pulled into retention
50 # state to reduce leakage energy further.
51 # Off: The logic block is power gated and is not consuming any energy.
52 class PwrState(Enum
): vals
= ['UNDEFINED',
58 class ClockedObject(SimObject
):
59 type = 'ClockedObject'
61 cxx_header
= "sim/clocked_object.hh"
63 # The clock domain this clocked object belongs to, inheriting the
64 # parent's clock domain by default
65 clk_domain
= Param
.ClockDomain(Parent
.clk_domain
, "Clock domain")
67 # Power model for this ClockedObject
68 power_model
= VectorParam
.PowerModel([], "Power models")
70 # Provide initial power state, should ideally get redefined in startup
72 default_p_state
= Param
.PwrState("UNDEFINED", "Default Power State")
74 p_state_clk_gate_min
= Param
.Latency('1ns',"Min value of the distribution")
75 p_state_clk_gate_max
= Param
.Latency('1s',"Max value of the distribution")
76 p_state_clk_gate_bins
= Param
.Unsigned('20',
77 "# bins in clk gated distribution")