src/sim/DVFSHandler.py

   1 # Copyright (c) 2013-2014 ARM Limited
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  35
  36 from m5.params import *
  37 from m5.SimObject import SimObject
  38 from m5.proxy import *
  39
  40 # The handler in its current form is design to be centeralized, one per system
  41 # and manages all the source clock domains (SrcClockDomain) it is configured to
  42 # handle.  The specific voltage and frequency points are configured per clock
  43 # and voltage domain.
  44 class DVFSHandler(SimObject):
  45     type = 'DVFSHandler'
  46     cxx_header = "sim/dvfs_handler.hh"
  47
  48     # List of controllable clock domains which in turn reference the appropriate
  49     # voltage domains
  50     domains = VectorParam.SrcClockDomain([], "list of domains")
  51
  52     # System domain (its clock and voltage) is not controllable
  53     sys_clk_domain = Param.SrcClockDomain(Parent.clk_domain,
  54                          "Clk domain in which the handler is instantiated")
  55
  56     enable = Param.Bool(False, "Enable/Disable the handler")
  57
  58     # The transition latency depends on how much time the PLLs and voltage
  59     # regualators takes to migrate from current levels to the new level, is
  60     # usally variable and hardware implementation dependent. In order to
  61     # accomodate this effect with ease, we provide a fixed transition latency
  62     # associated with all migrations. Configure this to maximum latency that
  63     # the hardware will take to migratate between any two perforamnce levels.
  64     transition_latency = Param.Latency('100us',
  65                              "fixed latency for perf level migration")