src/sim/DVFSHandler.py

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  36 # Authors: Vasileios Spiliopoulos
  37 #          Akash Bagdia
  38
  39 from m5.params import *
  40 from m5.SimObject import SimObject
  41 from m5.proxy import *
  42
  43 # The handler in its current form is design to be centeralized, one per system
  44 # and manages all the source clock domains (SrcClockDomain) it is configured to
  45 # handle.  The specific voltage and frequency points are configured per clock
  46 # and voltage domain.
  47 class DVFSHandler(SimObject):
  48     type = 'DVFSHandler'
  49     cxx_header = "sim/dvfs_handler.hh"
  50
  51     # List of controllable clock domains which in turn reference the appropriate
  52     # voltage domains
  53     domains = VectorParam.SrcClockDomain([], "list of domains")
  54
  55     # System domain (its clock and voltage) is not controllable
  56     sys_clk_domain = Param.SrcClockDomain(Parent.clk_domain,
  57                          "Clk domain in which the handler is instantiated")
  58
  59     enable = Param.Bool(False, "Enable/Disable the handler")
  60
  61     # The transition latency depends on how much time the PLLs and voltage
  62     # regualators takes to migrate from current levels to the new level, is
  63     # usally variable and hardware implementation dependent. In order to
  64     # accomodate this effect with ease, we provide a fixed transition latency
  65     # associated with all migrations. Configure this to maximum latency that
  66     # the hardware will take to migratate between any two perforamnce levels.
  67     transition_latency = Param.Latency('100us',
  68                              "fixed latency for perf level migration")