c9e4415f547adcee63cb0af7892257e988881363
[gem5.git] / src / sim / SConscript
1 # -*- mode:python -*-
2
3 # Copyright (c) 2006 The Regents of The University of Michigan
4 # All rights reserved.
5 #
6 # Redistribution and use in source and binary forms, with or without
7 # modification, are permitted provided that the following conditions are
8 # met: redistributions of source code must retain the above copyright
9 # notice, this list of conditions and the following disclaimer;
10 # redistributions in binary form must reproduce the above copyright
11 # notice, this list of conditions and the following disclaimer in the
12 # documentation and/or other materials provided with the distribution;
13 # neither the name of the copyright holders nor the names of its
14 # contributors may be used to endorse or promote products derived from
15 # this software without specific prior written permission.
16 #
17 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 #
29 # Authors: Nathan Binkert
30
31 Import('*')
32
33 SimObject('Root.py')
34 SimObject('System.py')
35 SimObject('InstTracer.py')
36
37 Source('async.cc')
38 Source('compile_info.cc')
39 Source('core.cc')
40 Source('debug.cc')
41 Source('eventq.cc')
42 Source('faults.cc')
43 Source('main.cc')
44 Source('root.cc')
45 Source('serialize.cc')
46 Source('sim_events.cc')
47 Source('sim_object.cc')
48 Source('simulate.cc')
49 Source('startup.cc')
50 Source('stat_control.cc')
51 Source('system.cc')
52
53 if env['FULL_SYSTEM']:
54 Source('arguments.cc')
55 Source('pseudo_inst.cc')
56 else:
57 Source('tlb.cc')
58 SimObject('Process.py')
59
60 Source('process.cc')
61 Source('syscall_emul.cc')
62
63 TraceFlag('Config')
64 TraceFlag('Event')
65 TraceFlag('Fault')
66 TraceFlag('Flow')
67 TraceFlag('IPI')
68 TraceFlag('IPR')
69 TraceFlag('Interrupt')
70 TraceFlag('Loader')
71 TraceFlag('Stack')
72 TraceFlag('SyscallVerbose')
73 TraceFlag('TLB')
74 TraceFlag('Thread')
75 TraceFlag('Timer')
76 TraceFlag('VtoPhys')