src/sim/SConscript

   1 # -*- mode:python -*-
   2
   3 # Copyright (c) 2006 The Regents of The University of Michigan
   4 # All rights reserved.
   5 #
   6 # Redistribution and use in source and binary forms, with or without
   7 # modification, are permitted provided that the following conditions are
   8 # met: redistributions of source code must retain the above copyright
   9 # notice, this list of conditions and the following disclaimer;
  10 # redistributions in binary form must reproduce the above copyright
  11 # notice, this list of conditions and the following disclaimer in the
  12 # documentation and/or other materials provided with the distribution;
  13 # neither the name of the copyright holders nor the names of its
  14 # contributors may be used to endorse or promote products derived from
  15 # this software without specific prior written permission.
  16 #
  17 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28 #
  29 # Authors: Nathan Binkert
  30
  31 Import('*')
  32
  33 SimObject('BaseTLB.py')
  34 SimObject('ClockedObject.py')
  35 SimObject('Root.py')
  36 SimObject('InstTracer.py')
  37
  38 Source('arguments.cc')
  39 Source('async.cc')
  40 Source('core.cc')
  41 Source('debug.cc')
  42 Source('eventq.cc')
  43 Source('init.cc')
  44 Source('main.cc', main=True, skip_lib=True)
  45 Source('root.cc')
  46 Source('serialize.cc')
  47 Source('sim_events.cc')
  48 Source('sim_object.cc')
  49 Source('simulate.cc')
  50 Source('stat_control.cc')
  51 Source('syscall_emul.cc')
  52
  53 if env['TARGET_ISA'] != 'no':
  54     SimObject('Process.py')
  55     SimObject('System.py')
  56     Source('faults.cc')
  57     Source('process.cc')
  58     Source('pseudo_inst.cc')
  59     Source('system.cc')
  60
  61 if env['TARGET_ISA'] != 'no':
  62     Source('tlb.cc')
  63
  64 DebugFlag('Checkpoint')
  65 DebugFlag('Config')
  66 DebugFlag('Drain')
  67 DebugFlag('Event')
  68 DebugFlag('Fault')
  69 DebugFlag('Flow')
  70 DebugFlag('IPI')
  71 DebugFlag('IPR')
  72 DebugFlag('Interrupt')
  73 DebugFlag('Loader')
  74 DebugFlag('Stack')
  75 DebugFlag('SyscallVerbose')
  76 DebugFlag('TimeSync')
  77 DebugFlag('TLB')
  78 DebugFlag('Thread')
  79 DebugFlag('Timer')
  80 DebugFlag('VtoPhys')
  81 DebugFlag('WorkItems')